Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   530 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
vl.c: Report unknown machines correctly vl.c: Report unknown machines correctly - - 1 - --- 2019-09-15 Palmer Dabbelt New
target/riscv: Zero extend the inputs of divuw and remuw target/riscv: Zero extend the inputs of divuw and remuw - - 1 - --- 2019-03-21 Palmer Dabbelt New
sifive_prci: Read and write PRCI registers sifive_prci: Read and write PRCI registers - - 2 - --- 2019-03-22 Palmer Dabbelt New
sifive_prci: Read and write PRCI registers sifive_prci: Read and write PRCI registers - - 1 - --- 2019-05-29 Palmer Dabbelt New
[v7,35/35] target/riscv: Remaining rvc insn reuse 32 bit translators target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,31/35] target/riscv: Convert @cs_2 insns to share translation functions target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,30/35] target/riscv: Remove decode_RV32_64G() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,29/35] target/riscv: Remove gen_system() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,28/35] target/riscv: Rename trans_arith to gen_arith target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,27/35] target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,26/35] target/riscv: Remove shift and slt insn manual decoding target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,23/35] target/riscv: Remove manual decoding from gen_store() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,22/35] target/riscv: Remove manual decoding from gen_load() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,21/35] target/riscv: Remove manual decoding from gen_branch() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,20/35] target/riscv: Remove gen_jalr() target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,16/35] target/riscv: Convert RV priv insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,15/35] target/riscv: Convert RV64D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,14/35] target/riscv: Convert RV32D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,13/35] target/riscv: Convert RV64F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,12/35] target/riscv: Convert RV32F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,11/35] target/riscv: Convert RV64A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,10/35] target/riscv: Convert RV32A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,09/35] target/riscv: Convert RVXM insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,08/35] target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,07/35] target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,06/35] target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,05/35] target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,04/35] target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,03/35] target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert to decodetree 1 - 2 - --- 2019-02-13 Palmer Dabbelt New
[v7,02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext target/riscv: Convert to decodetree - - 3 - --- 2019-02-13 Palmer Dabbelt New
[v2] RISC-V: Ignore the S and U letters when formatting ISA strings [v2] RISC-V: Ignore the S and U letters when formatting ISA strings - - 1 - --- 2019-08-13 Palmer Dabbelt New
[v2] RISC-V: Ignore the S and U extensions when formatting ISA strings [v2] RISC-V: Ignore the S and U extensions when formatting ISA strings - - - - --- 2019-08-07 Palmer Dabbelt New
[for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines [for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines - - - - --- 2018-11-21 Palmer Dabbelt New
[for-3.1,2/2] MAINTAINERS: Mark RISC-V as Supported Untitled series #77367 - - 1 - --- 2018-11-21 Palmer Dabbelt New
[for-3.1,1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file [for-3.1,1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file - - - - --- 2018-11-21 Palmer Dabbelt New
[for,4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings [for,4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings - - - - --- 2019-08-07 Palmer Dabbelt New
[for,3.1] RISC-V: Respect fences for user-only emulators [for,3.1] RISC-V: Respect fences for user-only emulators - - 2 - --- 2018-11-09 Palmer Dabbelt New
[PULL] target/riscv: Zero extend the inputs of divuw and remuw [PULL] target/riscv: Zero extend the inputs of divuw and remuw - - 1 - --- 2019-03-26 Palmer Dabbelt New
[PULL] target/riscv: Fix wrong expanding for c.fswsp [PULL] target/riscv: Fix wrong expanding for c.fswsp - - 1 - --- 2019-03-26 Palmer Dabbelt New
[PULL] target/riscv: Fix manually parsed 16 bit insn [PULL] target/riscv: Fix manually parsed 16 bit insn - - 1 2 --- 2019-03-18 Palmer Dabbelt New
[PULL] target/riscv: Convert to decodetree [PULL] target/riscv: Convert to decodetree - - - - --- 2019-03-01 Palmer Dabbelt New
[PULL] target/riscv: Convert to decodetree [PULL] target/riscv: Convert to decodetree - - - - --- 2019-03-12 Palmer Dabbelt New
[PULL] target/riscv: Convert to decodetree [PULL] target/riscv: Convert to decodetree - - - - --- 2019-03-13 Palmer Dabbelt New
[PULL] riscv: spike: Fix memory leak in the board init [PULL] riscv: spike: Fix memory leak in the board init - - 2 - --- 2018-11-08 Palmer Dabbelt New
[PULL] riscv/boot: Fixup the RISC-V firmware warning [PULL] riscv/boot: Fixup the RISC-V firmware warning - - 1 - --- 2019-07-26 Palmer Dabbelt New
[PULL] Update my MAINTAINERS file entry [PULL] Update my MAINTAINERS file entry - - - - --- 2019-11-01 Palmer Dabbelt New
[PULL] RISC-V Updates for 3.2, Part 2 [PULL] RISC-V Updates for 3.2, Part 2 - - - - --- 2019-01-11 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 - - - - --- 2019-10-28 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - - - --- 2019-07-03 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 - - - - --- 2019-06-28 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - - - --- 2019-06-27 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2 - - - - --- 2018-11-01 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.2-rc2 [PULL] RISC-V Patches for 4.2-rc2 - - - - --- 2019-07-19 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc3, v2 [PULL] RISC-V Patches for 4.0-rc3, v2 - - - - --- 2019-04-05 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc3 [PULL] RISC-V Patches for 4.0-rc3 - - - - --- 2019-04-04 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc0, Part 2 [PULL] RISC-V Patches for 4.0-rc0, Part 2 - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL] RISC-V Patches for 3.2, Part 3 [PULL] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL] RISC-V Patches for 3.1-rc2 [PULL] RISC-V Patches for 3.1-rc2 - - - - --- 2018-11-16 Palmer Dabbelt New
[PULL] RISC-V Patch for 4.1-rc3 [PULL] RISC-V Patch for 4.1-rc3 - - - - --- 2019-07-26 Palmer Dabbelt New
[PULL] RISC-V Changes for 3.2, Part 1 [PULL] RISC-V Changes for 3.2, Part 1 - - - - --- 2018-12-26 Palmer Dabbelt New
[PULL] MAINTAINERS: Change to my personal email address [PULL] MAINTAINERS: Change to my personal email address - - 1 - --- 2019-11-01 Palmer Dabbelt New
[PULL] First RISC-V Patch Set for the 3.1 Soft Freeze [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze - - - - --- 2018-10-17 Palmer Dabbelt New
[PULL] A second RISC-V Patch for 4.0.0-rc1 [PULL] A second RISC-V Patch for 4.0.0-rc1 - - - - --- 2019-03-26 Palmer Dabbelt New
[PULL] A Single RISC-V Patch for 4.0-rc1 [PULL] A Single RISC-V Patch for 4.0-rc1 - - - - --- 2019-03-26 Palmer Dabbelt New
[PULL] A Single RISC-V Patch for 4.0-rc0 [PULL] A Single RISC-V Patch for 4.0-rc0 - - - - --- 2019-03-18 Palmer Dabbelt New
[PULL] A Single RISC-V Patch for 3.1-rc1 [PULL] A Single RISC-V Patch for 3.1-rc1 - - - - --- 2018-11-08 Palmer Dabbelt New
[PULL,5/5] RISC-V: Don't add NULL bootargs to device-tree [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze - - 3 - --- 2018-10-17 Palmer Dabbelt New
[PULL,48/48] gdbstub: riscv: fix the fflags registers [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,46/48] target/riscv: Fix mstatus dirty mask [PULL,01/48] riscv: sifive_u: Add support for loading initrd - 1 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,46/47] target/riscv: Fix mstatus dirty mask [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,45/48] target/riscv: Use both register name and ABI name [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,45/47] target/riscv: Use both register name and ABI name [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,44/48] riscv: sifive_u: Update model and compatible strings in device tree [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,44/47] riscv: sifive_u: Update model and compatible strings in device tree [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,42/48] riscv: sifive_u: Fix broken GEM support [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,42/47] riscv: sifive_u: Fix broken GEM support [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,41/48] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,41/47] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,40/48] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,40/47] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,4/5] RISC-V: Add missing free for plic_hart_config Untitled series #71320 - - 3 - --- 2018-10-17 Palmer Dabbelt New
[PULL,4/4] default-configs: Enable USB support for RISC-V machines [PULL] RISC-V Updates for 3.2, Part 2 - - - - --- 2019-01-11 Palmer Dabbelt New
[PULL,4/4] RISC-V: Respect fences for user-only emulators [PR,RFC] RISC-V Patches for 3.1-rc2 - - 3 - --- 2018-11-13 Palmer Dabbelt New
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