| Message ID | 20190318052759.10860-1-palmer@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [PULL] A Single RISC-V Patch for 4.0-rc0 | expand |
On Mon, 18 Mar 2019 at 05:28, Palmer Dabbelt <palmer@sifive.com> wrote: > > The following changes since commit d4e65539e570d5872003710b5a1064489911d33d: > > Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into staging (2019-03-17 14:10:52 +0000) > > are available in the Git repository at: > > git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0 > > for you to fetch changes up to f330433b3633647b047cfa418c2ca4d18fda69c7: > > target/riscv: Fix manually parsed 16 bit insn (2019-03-17 22:21:32 -0700) > > ---------------------------------------------------------------- > A Single RISC-V Patch for 4.0-rc0 > > There was a regression introduced by the decodetree conversion that has > a fairly straight-forward fix. Since this fixes bugs that everyone has > hit I'd like to target it for rc0. > > ---------------------------------------------------------------- > Bastian Koppelmann (1): > target/riscv: Fix manually parsed 16 bit insn > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0 for any user-visible changes. -- PMM
The following changes since commit d4e65539e570d5872003710b5a1064489911d33d: Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into staging (2019-03-17 14:10:52 +0000) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0 for you to fetch changes up to f330433b3633647b047cfa418c2ca4d18fda69c7: target/riscv: Fix manually parsed 16 bit insn (2019-03-17 22:21:32 -0700) ---------------------------------------------------------------- A Single RISC-V Patch for 4.0-rc0 There was a regression introduced by the decodetree conversion that has a fairly straight-forward fix. Since this fixes bugs that everyone has hit I'd like to target it for rc0. ---------------------------------------------------------------- Bastian Koppelmann (1): target/riscv: Fix manually parsed 16 bit insn target/riscv/insn_trans/trans_rvc.inc.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-)