Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   530 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
Add Alistair as a RISC-V Maintainer Add Alistair as a RISC-V Maintainer - - 2 - --- 2018-10-29 Palmer Dabbelt New
Add qemu-riscv@nongnu.org as the RISC-V list Add qemu-riscv@nongnu.org as the RISC-V list - - 2 1 --- 2018-10-30 Palmer Dabbelt New
MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer - - - - --- 2019-01-25 Palmer Dabbelt New
RISC-V: Add support for the Zicsr extension RISC-V: Add support for the Zicsr extension - - 1 - --- 2019-06-25 Palmer Dabbelt New
RISC-V: Add support for the Zifencei extension RISC-V: Add support for the Zifencei extension - - - - --- 2019-06-25 Palmer Dabbelt New
RISC-V: Fix a memory leak when realizing a sifive_e RISC-V: Fix a memory leak when realizing a sifive_e - 1 2 - --- 2019-06-14 Palmer Dabbelt New
RISC-V: fcvt can set fflags, so set FS accordingly RISC-V: fcvt can set fflags, so set FS accordingly - - 1 - --- 2019-10-09 Palmer Dabbelt New
RISC-V: virt: This is a "sifive,test1" test finisher RISC-V: virt: This is a "sifive,test1" test finisher - 1 1 - --- 2019-11-07 Palmer Dabbelt New
[PR,RFC] RISC-V Changes for 3.2, Part 1 [PR,RFC] RISC-V Changes for 3.2, Part 1 - - - - --- 2018-12-21 Palmer Dabbelt New
[PR,RFC] RISC-V Patches for 3.1-rc2 [PR,RFC] RISC-V Patches for 3.1-rc2 - - - - --- 2018-11-13 Palmer Dabbelt New
[PR,RFC] RISC-V Patches for 3.2, Part 3 [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
[PR,RFC] RISC-V Patches for the 3.1 Soft Freeze, Part 2 [PR,RFC] RISC-V Patches for the 3.1 Soft Freeze, Part 2 - - - - --- 2018-10-30 Palmer Dabbelt New
[PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts [PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - - 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts [PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - - 2 --- 2018-12-21 Palmer Dabbelt New
[PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,01/19] RISC-V: Add 32-bit gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,01/29] SiFive RISC-V GPIO Device [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-13 Palmer Dabbelt New
[PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-12 Palmer Dabbelt New
[PULL,01/32] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/32] target/riscv: Allow setting ISA extensions via CPU props - - - - --- 2019-07-03 Palmer Dabbelt New
[PULL,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC [PULL,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - - --- 2019-06-28 Palmer Dabbelt New
[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - - --- 2019-06-27 Palmer Dabbelt New
[PULL,01/47] riscv: sifive_u: Add support for loading initrd [PULL,01/47] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,01/48] riscv: sifive_u: Add support for loading initrd [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,02/10] RISC-V: Mark mstatus.fs dirty [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,02/10] RISC-V: Mark mstatus.fs dirty [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,02/11] RISC-V: Mark mstatus.fs dirty Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PULL] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-21 Palmer Dabbelt New
[PULL,02/18] RISC-V: Handle bus errors in the page table walker [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,02/19] RISC-V: Add 64-bit gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,02/29] target/riscv: Convert RVXI branch insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 2 - --- 2019-03-13 Palmer Dabbelt New
[PULL,02/29] target/riscv: Convert RVXI branch insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 2 - --- 2019-03-12 Palmer Dabbelt New
[PULL,02/29] target/riscv: Do not allow sfence.vma from user mode [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,02/32] sifive_prci: Read and write PRCI registers [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,02/34] sifive_prci: Read and write PRCI registers [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,02/34] sifive_prci: Read and write PRCI registers [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,02/34] target/riscv: Convert RVXI branch insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 2 - --- 2019-03-01 Palmer Dabbelt New
[PULL,02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Untitled series #131345 - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,03/10] RISC-V: Implement mstatus.TSR/TW/TVM [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,03/10] RISC-V: Implement mstatus.TSR/TW/TVM [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
[PULL,03/11] RISC-V: Implement mstatus.TSR/TW/TVM Untitled series #91747 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PULL] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-21 Palmer Dabbelt New
[PULL,03/18] RISC-V: Implement cpu_do_transaction_failed [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,03/19] RISC-V: Fixes to CSR_* register macros. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,03/29] RISC-V: fix single stepping over ret and other branching instructions [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,03/29] target/riscv: Convert RV32I load/store insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-13 Palmer Dabbelt New
[PULL,03/29] target/riscv: Convert RV32I load/store insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-12 Palmer Dabbelt New
[PULL,03/32] target/riscv: Fix PMP range boundary address bug [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - 2 - --- 2019-07-03 Palmer Dabbelt New
[PULL,03/34] target/riscv: Convert RV32I load/store insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 2 - --- 2019-06-27 Palmer Dabbelt New
[PULL,03/47] riscv: sifive_u: Fix clock-names property for ethernet node [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,03/48] riscv: sifive_u: Fix clock-names property for ethernet node [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,04/10] RISC-V: Use riscv prefix consistently on cpu helpers [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,04/10] RISC-V: Use riscv prefix consistently on cpu helpers [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,04/11] RISC-V: Use riscv prefix consistently on cpu helpers Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA [PULL] RISC-V Changes for 3.2, Part 1 - - 1 1 --- 2018-12-26 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 1 --- 2018-12-21 Palmer Dabbelt New
[PULL,04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,04/19] RISC-V: Add debug support for accessing CSRs. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,04/29] target/riscv: Convert RV64I load/store insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-13 Palmer Dabbelt New
[PULL,04/29] target/riscv: Convert RV64I load/store insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-12 Palmer Dabbelt New
[PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,04/32] target/riscv: Implement riscv_cpu_unassigned_access [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,04/34] target/riscv: Convert RV64I load/store insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,05/10] RISC-V: Add priv_ver to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,05/10] RISC-V: Add priv_ver to DisasContext [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,05/11] RISC-V: Add priv_ver to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,05/18] riscv: sifive_u: Add ethernet0 to the aliases node [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,05/19] RISC-V: Add hooks to use the gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-13 Palmer Dabbelt New
[PULL,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-12 Palmer Dabbelt New
[PULL,05/29] target/riscv: Use --static-decode for decodetree [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,05/32] RISC-V: Only Check PMP if MMU translation succeeds [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [PULL] target/riscv: Convert to decodetree 1 - 1 - --- 2019-03-01 Palmer Dabbelt New
[PULL,05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL,01/48] riscv: sifive_u: Add support for loading initrd - - 1 - --- 2019-09-18 Palmer Dabbelt New
[PULL,06/10] RISC-V: Add misa to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,06/10] RISC-V: Add misa to DisasContext [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,06/11] RISC-V: Add misa to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,06/18] linux-user/riscv: Propagate fault address [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,06/19] riscv: pmp: Log pmp access errors as guest errors [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,06/29] target/riscv: Convert RVXI fence insns to decodetree [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 - 1 - --- 2019-03-13 Palmer Dabbelt New
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