Show patches with: Archived = No       |   339249 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
Virtio-net: Replace the hardcode 6 with defined ETN_ALEN - - - - --- 2010-05-23 Amos Kong aliguori Accepted
vhost-user: only set slave channel for first vq vhost-user: only set slave channel for first vq - 1 - - --- 2020-01-21 Adrian Moreno mst New
[v3] vhost-user: save features if the char dev is closed [v3] vhost-user: save features if the char dev is closed 1 1 - - --- 2019-09-24 Adrian Moreno mst New
[v2,5/5] pl031: switch clock base to rtc_clock - - - - --- 2012-03-05 Paolo Bonzini pm215 New
[v2,4/5] pl031: rearm alarm timer upon load - - - - --- 2012-03-05 Paolo Bonzini pm215 New
[v2,3/5] arm: switch real-time clocks to rtc_clock - - - - --- 2012-03-05 Paolo Bonzini pm215 New
[v2,2/5] omap: switch omap_lpg to vm_clock - - - - --- 2012-03-05 Paolo Bonzini pm215 New
[v2,1/5] rtc: add -rtc clock=rt - - - - --- 2012-03-05 Paolo Bonzini pm215 New
[v2,5/5] sgx: Reset the vEPC regions during VM reboot SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,4/5] doc: Add the SGX numa description SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,3/5] numa: Support SGX numa in the monitor and Libvirt interfaces SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,2/5] monitor: Support 'info numa' command SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,1/5] numa: Enable numa for SGX EPC sections SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v16,8/8,RISCV_PM] Allow experimental J-ext to be turned on RISC-V Pointer Masking implementation - - 3 - --- 2021-10-22 Alexey Baturo New
[v16,7/8,RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension RISC-V Pointer Masking implementation - - 2 - --- 2021-10-22 Alexey Baturo New
[v16,6/8,RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions RISC-V Pointer Masking implementation - - 2 - --- 2021-10-22 Alexey Baturo New
[v16,5/8,RISCV_PM] Print new PM CSRs in QEMU logs RISC-V Pointer Masking implementation - - - - --- 2021-10-22 Alexey Baturo New
[v16,4/8,RISCV_PM] Add J extension state description RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,3/8,RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,2/8,RISCV_PM] Add CSR defines for RISC-V PM extension RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,1/8,RISCV_PM] Add J-extension into RISC-V RISC-V Pointer Masking implementation - - 3 - --- 2021-10-22 Alexey Baturo New
[3/3] target/mips: Fix Loongson-3A4000 MSAIR config register target/mips: MSA opcode fixes - - - - --- 2021-10-22 Philippe Mathieu-Daudé New
[2/3] target/mips: Fix MSA MSUBV.B opcode target/mips: MSA opcode fixes - 1 1 - --- 2021-10-22 Philippe Mathieu-Daudé New
[1/3] target/mips: Fix MSA MADDV.B opcode target/mips: MSA opcode fixes - 1 1 - --- 2021-10-22 Philippe Mathieu-Daudé New
[v4] isa-applesmc: provide OSK forwarding on Apple hosts [v4] isa-applesmc: provide OSK forwarding on Apple hosts - - - - --- 2021-10-22 Vladislav Yaroshchuk New
[v3,3/3] contrib/plugins: add a drcov plugin plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[v3,2/3] This patch adds helper functions to the drcov plugin. plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[v3,1/3] src/plugins: sorted list plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[PULL,33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,27/33] hw/intc: sifive_plic: Cleanup the irq_request function [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,26/33] hw/intc: sifive_plic: Cleanup the realize function [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,25/33] hw/intc: sifive_plic: Move the properties [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,24/33] hw/intc: Remove the Ibex PLIC [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,23/33] hw/riscv: opentitan: Update to the latest build [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,22/33] target/riscv: Compute mstatus.sd on demand [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,19/33] target/riscv: Use gen_unary_per_ol for RVB [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,18/33] target/riscv: Adjust trans_rev8_32 for riscv64 [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v 1 - 1 - --- 2021-10-22 Alistair Francis New
[PULL,17/33] target/riscv: Use gen_arith_per_ol for RVM [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,16/33] target/riscv: Replace DisasContext.w with DisasContext.ol [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,15/33] target/riscv: Replace is_32bit with get_xl/get_xlen [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,14/33] target/riscv: Properly check SEW in amo_op [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,13/33] target/riscv: Use REQUIRE_64BIT in amo_check64 [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,10/33] target/riscv: Split misa.mxl and misa.ext [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,09/33] target/riscv: Create RISCVMXL enumeration [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,08/33] target/riscv: Move cpu_get_tb_cpu_state out of line [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,07/33] target/riscv: Organise the CPU properties [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,06/33] target/riscv: Remove some unused macros [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,04/33] hw/riscv: virt: Use machine->ram as the system memory [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,03/33] target/riscv: Fix orc.b implementation [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - 1 1 1 --- 2021-10-22 Alistair Francis New
[PULL,02/33] target/riscv: line up all of the registers in the info register dump [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,00/33] riscv-to-apply queue - - - - --- 2021-10-22 Alistair Francis New
[PULL,1/2] update seabios to master branch snapshot [PULL,1/2] update seabios to master branch snapshot - - - - --- 2021-10-22 Gerd Hoffmann New
[PULL,0/2] Seabios 20211022 patches - - - - --- 2021-10-22 Gerd Hoffmann New
[v3] isa-applesmc: provide OSK forwarding on Apple hosts [v3] isa-applesmc: provide OSK forwarding on Apple hosts - - - - --- 2021-10-22 Vladislav Yaroshchuk New
[v2] isa-applesmc: provide OSK forwarding on Apple hosts [v2] isa-applesmc: provide OSK forwarding on Apple hosts - - - - --- 2021-10-22 Vladislav Yaroshchuk New
[RFC] plugins: try and make plugin_insn_append more ergonomic [RFC] plugins: try and make plugin_insn_append more ergonomic - - - - --- 2021-10-22 Alex Bennée New
block/export/fuse.c: fix musl build block/export/fuse.c: fix musl build - 1 - - --- 2021-10-22 Fabrice Fontaine New
[PULL,3/3] speed/sdhci: Add trace events [PULL,1/3] aspeed: Add support for the fp5280g2-bmc board - - 2 - --- 2021-10-22 Cédric Le Goater New
[PULL,2/3] aspeed/smc: Use a container for the flash mmio address space [PULL,1/3] aspeed: Add support for the fp5280g2-bmc board - - 2 - --- 2021-10-22 Cédric Le Goater New
[PULL,1/3] aspeed: Add support for the fp5280g2-bmc board [PULL,1/3] aspeed: Add support for the fp5280g2-bmc board - - 1 - --- 2021-10-22 Cédric Le Goater New
[PULL,0/3] aspeed queue - - - - --- 2021-10-22 Cédric Le Goater New
[PULL,9/9] q800: drop 8-bit graphic_depth check for Apple 21 inch display [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - 1 - - --- 2021-10-22 Laurent Vivier New
[PULL,8/9] q800: add NMI handler [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - - - --- 2021-10-22 Laurent Vivier New
[PULL,7/9] q800: wire up remaining IRQs in classic mode [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,6/9] q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,5/9] q800: wire up auxmode GPIO to GLUE [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,4/9] mac_via: add GPIO for A/UX mode [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,3/9] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,2/9] q800: move VIA1 IRQ from level 1 to level 6 [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,1/9] mac_via: update comment for VIA1B_vMystery bit [PULL,1/9] mac_via: update comment for VIA1B_vMystery bit - - 1 - --- 2021-10-22 Laurent Vivier New
[PULL,0/9] Q800 patches - - - - --- 2021-10-22 Laurent Vivier New
[v2,5/5] hw/riscv: virt: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,3/5] hw/riscv: sifive_u: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,2/5] hw/riscv: boot: Add a PLIC config string function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-22 Alistair Francis New
[v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-22 Alistair Francis New
[v3,48/48] tcg/optimize: Propagate sign info for shifting tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,47/48] tcg/optimize: Propagate sign info for bit counting tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,46/48] tcg/optimize: Propagate sign info for setcond tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,45/48] tcg/optimize: Propagate sign info for logical operations tcg: optimize redundant sign extensions - - 1 - --- 2021-10-21 Richard Henderson New
[v3,44/48] tcg/optimize: Optimize sign extensions tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,42/48] tcg/optimize: Add more simplifications for orc tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,41/48] tcg/optimize: Sink commutative operand swapping into fold functions tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops tcg: optimize redundant sign extensions - - 1 - --- 2021-10-21 Richard Henderson New
[v3,39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies tcg: optimize redundant sign extensions - - 1 - --- 2021-10-21 Richard Henderson New
[v3,38/48] tcg/optimize: Split out fold_masks tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,37/48] tcg/optimize: Split out fold_ix_to_i tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
[v3,36/48] tcg/optimize: Split out fold_xi_to_x tcg: optimize redundant sign extensions - - - - --- 2021-10-21 Richard Henderson New
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