Show patches with: Submitter = Jim Shu       |    State = Action Required       |    Archived = No       |   14 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[2/2] target/riscv: Make the "virt" register writable by GDB [1/2] target/riscv: Expose "virt" register for GDB for reads - - 2 - --- 2023-03-05 Jim Shu New
[1/2] target/riscv: Expose "virt" register for GDB for reads [1/2] target/riscv: Expose "virt" register for GDB for reads - - 3 - --- 2023-03-05 Jim Shu New
hw/intc: sifive_plic: fix out-of-bound access of source_priority array hw/intc: sifive_plic: fix out-of-bound access of source_priority array - - 1 - --- 2022-11-27 Jim Shu New
target/riscv: support cache-related PMU events in virtual mode target/riscv: support cache-related PMU events in virtual mode - - 1 - --- 2022-11-23 Jim Shu New
[v3,2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Enhance maximum priority support of PLIC 1 - 1 - --- 2022-10-03 Jim Shu New
[v3,1/2] hw/intc: sifive_plic: fix hard-coded max priority level Enhance maximum priority support of PLIC 1 - 1 - --- 2022-10-03 Jim Shu New
[v2,2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Enhance maximum priority support of PLIC - - - - --- 2022-09-30 Jim Shu New
[v2,1/2] hw/intc: sifive_plic: fix hard-coded max priority level Enhance maximum priority support of PLIC - - 1 - --- 2022-09-30 Jim Shu New
hw/intc: sifive_plic: fix hard-coded max priority level hw/intc: sifive_plic: fix hard-coded max priority level - - 1 - --- 2022-09-25 Jim Shu New
target/riscv: Support SW update of PTE A/D bits and Ssptwad extension target/riscv: Support SW update of PTE A/D bits and Ssptwad extension - - 1 - --- 2022-07-18 Jim Shu New
[v2,2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Align SiFive PDMA behavior to real hardware - - 4 1 --- 2022-01-04 Jim Shu New
[v2,1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Align SiFive PDMA behavior to real hardware - - 3 1 --- 2022-01-04 Jim Shu New
[2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Align SiFive PDMA behavior to real hardware - - 4 1 --- 2021-12-28 Jim Shu New
[1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Align SiFive PDMA behavior to real hardware - - 3 1 --- 2021-12-28 Jim Shu New