Show patches with: State = Action Required       |    Archived = No       |   335550 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[5/5] hw/sh4: Coding style: Remove unnecessary casts hw/sh4: Codeing style fixes - - - - --- 2021-10-24 BALATON Zoltan New
[2/5] hw/sh4: Coding style: Fix multi-line comments hw/sh4: Codeing style fixes - - - - --- 2021-10-24 BALATON Zoltan New
[3/5] hw/sh4: Coding style: White space fixes hw/sh4: Codeing style fixes - - - - --- 2021-10-24 BALATON Zoltan New
[1/5] hw/sh4: Coding style: Remove tabs hw/sh4: Codeing style fixes - - - - --- 2021-10-24 BALATON Zoltan New
[4/5] hw/sh4: Coding style: Add missing braces hw/sh4: Codeing style fixes - - - - --- 2021-10-24 BALATON Zoltan New
[33/33] target/mips: Adjust style in msa_translate_init() target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[32/33] target/mips: Remove one MSA unnecessary decodetree overlap group target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[31/33] target/mips: Remove generic MSA opcode target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[29/33] target/mips: Convert MSA MOVE.V opcode to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[27/33] target/mips: Convert MSA COPY_U opcode to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[26/33] target/mips: Convert MSA ELM instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[19/33] target/mips: Convert MSA VEC instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[18/33] target/mips: Convert MSA 2R instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[17/33] target/mips: Convert MSA FILL opcode to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[16/33] target/mips: Convert MSA 2RF instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[15/33] target/mips: Convert MSA load/store instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[14/33] target/mips: Convert MSA I8 instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[13/33] target/mips: Convert MSA SHF opcode to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[12/33] target/mips: Convert MSA BIT instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[11/33] target/mips: Convert MSA I5 instruction format to decodetree target/mips: Fully convert MSA opcodes to decodetree - - 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
[10/33] target/mips: Extract df_extract() helper target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[08/33] target/mips: Convert MSA LDI opcode to decodetree target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v target/mips: Fully convert MSA opcodes to decodetree - - 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
[06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum target/mips: Fully convert MSA opcodes to decodetree - - 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
[05/33] target/mips: Have check_msa_access() return a boolean target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation target/mips: Fully convert MSA opcodes to decodetree - - - - --- 2021-10-23 Philippe Mathieu-Daudé New
[03/33] target/mips: Fix MSA MSUBV.B opcode target/mips: Fully convert MSA opcodes to decodetree - 1 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
[02/33] target/mips: Fix MSA MADDV.B opcode target/mips: Fully convert MSA opcodes to decodetree - 1 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
[01/33] tests/tcg: Fix some targets default cross compiler path target/mips: Fully convert MSA opcodes to decodetree - 1 1 - --- 2021-10-23 Philippe Mathieu-Daudé New
linux-user/signal: Map exit signals in SIGCHLD siginfo_t linux-user/signal: Map exit signals in SIGCHLD siginfo_t - - - - --- 2021-10-23 Matthias Schiffer New
[PULL,11/11] analyze-migration.py: fix extract contents ('-x') errors [PULL,01/11] po: update turkish translation - - 1 - --- 2021-10-23 Laurent Vivier New
[PULL,10/11] analyze-migration.py: fix a long standing typo [PULL,01/11] po: update turkish translation - 1 1 - --- 2021-10-23 Laurent Vivier New
[PULL,09/11] README: Fix some documentation URLs [PULL,01/11] po: update turkish translation - - 1 1 --- 2021-10-23 Laurent Vivier New
[PULL,08/11] hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device [PULL,01/11] po: update turkish translation - - 3 - --- 2021-10-23 Laurent Vivier New
[PULL,07/11] hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device [PULL,01/11] po: update turkish translation - - 3 - --- 2021-10-23 Laurent Vivier New
[PULL,06/11] hw/nvram: Fix Memory Leak in Xilinx eFuse QOM [PULL,01/11] po: update turkish translation - - 3 - --- 2021-10-23 Laurent Vivier New
[PULL,05/11] softmmu/physmem.c: Fix typo in comment [PULL,01/11] po: update turkish translation - - 1 - --- 2021-10-23 Laurent Vivier New
[PULL,04/11] MAINTAINERS: Add myself as reviewer of 'Machine core' API [PULL,01/11] po: update turkish translation - - - - --- 2021-10-23 Laurent Vivier New
[PULL,03/11] disas/nios2: Simplify endianess conversion [PULL,01/11] po: update turkish translation - - 2 - --- 2021-10-23 Laurent Vivier New
[PULL,02/11] disas/nios2: Fix style in print_insn_nios2() [PULL,01/11] po: update turkish translation - - 2 - --- 2021-10-23 Laurent Vivier New
[PULL,01/11] po: update turkish translation [PULL,01/11] po: update turkish translation - - 1 - --- 2021-10-23 Laurent Vivier New
[PULL,00/11] Trivial branch for 6.2 patches - - - - --- 2021-10-23 Laurent Vivier New
tests/tcg: Fix some targets default cross compiler path tests/tcg: Fix some targets default cross compiler path - 1 - - --- 2021-10-23 Philippe Mathieu-Daudé New
[v3,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,09/22] target/riscv: Implement AIA local interrupt priorities QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,04/22] target/riscv: Improve delivery of guest external interrupts QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 1 - --- 2021-10-23 Anup Patel New
[v2,5/5] sgx: Reset the vEPC regions during VM reboot SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,4/5] doc: Add the SGX numa description SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,3/5] numa: Support SGX numa in the monitor and Libvirt interfaces SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,2/5] monitor: Support 'info numa' command SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v2,1/5] numa: Enable numa for SGX EPC sections SGX NUMA support plus vepc reset - - - - --- 2021-10-22 Yang Zhong New
[v16,8/8,RISCV_PM] Allow experimental J-ext to be turned on RISC-V Pointer Masking implementation - - 3 - --- 2021-10-22 Alexey Baturo New
[v16,7/8,RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension RISC-V Pointer Masking implementation - - 2 - --- 2021-10-22 Alexey Baturo New
[v16,6/8,RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions RISC-V Pointer Masking implementation - - 2 - --- 2021-10-22 Alexey Baturo New
[v16,5/8,RISCV_PM] Print new PM CSRs in QEMU logs RISC-V Pointer Masking implementation - - - - --- 2021-10-22 Alexey Baturo New
[v16,4/8,RISCV_PM] Add J extension state description RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,3/8,RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,2/8,RISCV_PM] Add CSR defines for RISC-V PM extension RISC-V Pointer Masking implementation - - 1 - --- 2021-10-22 Alexey Baturo New
[v16,1/8,RISCV_PM] Add J-extension into RISC-V RISC-V Pointer Masking implementation - - 3 - --- 2021-10-22 Alexey Baturo New
[3/3] target/mips: Fix Loongson-3A4000 MSAIR config register target/mips: MSA opcode fixes - - 1 - --- 2021-10-22 Philippe Mathieu-Daudé New
[2/3] target/mips: Fix MSA MSUBV.B opcode target/mips: MSA opcode fixes - 1 1 - --- 2021-10-22 Philippe Mathieu-Daudé New
[1/3] target/mips: Fix MSA MADDV.B opcode target/mips: MSA opcode fixes - 1 1 - --- 2021-10-22 Philippe Mathieu-Daudé New
[v4] isa-applesmc: provide OSK forwarding on Apple hosts [v4] isa-applesmc: provide OSK forwarding on Apple hosts - - - - --- 2021-10-22 Vladislav Yaroshchuk New
[v3,3/3] contrib/plugins: add a drcov plugin plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[v3,2/3] This patch adds helper functions to the drcov plugin. plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[v3,1/3] src/plugins: sorted list plugins: add a drcov plugin - - - - --- 2021-10-22 NDNF New
[PULL,33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
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