diff mbox

[OpenWrt-Devel,3/5] ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x

Message ID 1597896.C7H9vtOXix@bentobox
State Not Applicable
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Commit Message

Sven Eckelmann March 17, 2016, 10:26 a.m. UTC 
On Thursday 17 March 2016 09:19:49 Sven Eckelmann wrote:
> On Wednesday 16 March 2016 22:41:58 Christian Beier wrote:
> > Am Tue,  8 Mar 2016 18:39:05 +0100
> > schrieb Sven Eckelmann <sven.eckelmann@open-mesh.com>:
> > 
> > > The default RGMII values from the Atheros u-boot are currently used to
> > > preset the existing mach files. These may have to be adjusted for boards
> > > using different values but which are not currently set them explicitely in
> > > OpenWrt.
> > 
> > Hi Sven,
> > 
> > Just to clarify: If I don't have any special values than the presets are used
> > and there's nothing I have to do in that case?
> 
> You have to find out what values are working (for example by checking what
> u-boot currently sets in ETH_CFG before ath79_setup_qca955x_eth_cfg overwrites
> it). But it looks that John doesn't like that mach-* files correctly set the
> content of ETH_CFG via this function.

Before there is a misunderstanding: I have no problem with
ath79_setup_qca955x_eth_cfg not changing its current behavior. There are already
mach-* files doing their own thing with ETH_CFG because OpenWrt didn't want to
change the current behavior of it and I will just do the same for some upcoming
mach-* files (and then also for mr1750/mr900).

> So you don't have to do anything and just
> hope that u-boot does always the right (which it doesn't do here, for example
> booting up with 100Base-T Full Duplex and then switching to 1000Base-T full
> duplex under OpenWrt doesn't work for MR1750 and some other products I had in
> my hand).

Attached is a small hack to show you the preset values by u-boot for QCA955x.
Just in case you are interested in finding out what your u-boot sets when
booting up with different link speeds. Apply the patch (currently for
f51f2b3e7b18/r49031), attach the device directly to a different PC and boot
your device up. You should see some XXXXXX with the old and new pll_* values
for the selected speed (only the first "old" values for xmii/sgmii are
interesting) and QCA955X_GMAC_REG_ETH_CFG-pre with the values set by u-boot.

This procedure can be repeated with different speeds. Just set the linkspeed
(1000, 100, 10) on your PC via:

    ethtool -s eth0 speed 1000 duplex full

and then power up the device again. You should check out
https://dev.openwrt.org/changeset/49027/trunk for the known bits in
QCA955X_GMAC_REG_ETH_CFG.

You can also manipulate this register directly from userspace. Just enable
the busybox tool devmem and enable the /dev/mem support code in
target/linux/generic/config-4.* (CONFIG_DEVKMEM=y, CONFIG_DEVMEM=y). The
currently set value for ETH_CFG on QCA955x can be read via:

    devmem 0x18070000 32

and written via (just a dummy example value):

    devmem 0x18070000 32 0x12345678

Kind regards,
	Sven

Comments

John Crispin March 17, 2016, 10:53 a.m. UTC | #1 
On 17/03/2016 11:26, Sven Eckelmann wrote:
> But it looks that John doesn't like that mach-* files correctly set the
>> content of ETH_CFG via this function.

i like it if it is consistent. the current patch lead to people sending
me mails that their boards no longer work ;)

people like to point at others for the fault i like to just have rough
consensus and running code and this code in this state is not running
properly. its not my choice or opinion, its a simple matter of "does not
work"
diff mbox

Patch

From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Date: Tue, 8 Mar 2016 16:20:54 +0100
Subject: [PATCH] Print PLL/ETH_CFG INFOs
---
 target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 6445023..f4ec450 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -377,8 +377,11 @@  static void qca955x_set_speed_xmii(int speed)
 {
 	void __iomem *base;
 	u32 val = ath79_get_eth_pll(0, speed);
+	u32 t;
 
 	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+	t = __raw_readl(base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
+	printk("XXXXXX %s:%u old %08x new %08x\n", __func__, __LINE__, t, val);
 	__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
 	iounmap(base);
 }
@@ -387,8 +390,11 @@  static void qca955x_set_speed_sgmii(int speed)
 {
 	void __iomem *base;
 	u32 val = ath79_get_eth_pll(1, speed);
+	u32 t;
 
 	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+	t = __raw_readl(base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
+	printk("XXXXXX %s:%u old %08x new %08x\n", __func__, __LINE__, t, val);
 	__raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
 	iounmap(base);
 }
@@ -855,6 +861,7 @@  void __init ath79_setup_qca955x_eth_cfg(u32 mask,
 	base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 
 	t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+	printk("QCA955X_GMAC_REG_ETH_CFG-pre %08x\n", t);
 
 	t &= ~m;
 	t |= mask;
@@ -863,6 +870,8 @@  void __init ath79_setup_qca955x_eth_cfg(u32 mask,
 	t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
 	t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
 
+	printk("QCA955X_GMAC_REG_ETH_CFG-post %08x\n", t);
+
 	__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 
 	iounmap(base);