| Message ID | 1441768771-18567-1-git-send-email-hackpascal@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Weijie Gao <hackpascal@gmail.com> wrote: > Signed-off-by: Weijie Gao <hackpascal@gmail.com> > > According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz > input clock as the REF_CLK instead of 5MHz. > > The correct CPU PLL calculation procedure is as follows: > CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. > > This patch is compatible with the current calculation procedure with > default > DIV and REF_DIV values. > > Test on both AR7240, AR7241 and AR7242. So, what was the behaviour before? Cheers, Karl P -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJV8ZUHAAoJEBmotQ/U1cr2aAAP/iPniiHKY/hEKqriniqdWdvE y9e9gs48KcYxBt5wHninUK1Jsz3Gc1qzpsuyfxxWS6yuZvqMeSnR1UBnH9ztbRQM ZvXKS79GhCEQkdBlZL74RBqVaBGz0lQ59La7b4NRTmPfKV5HQdZpo51EaA/iNOwT 6iy1w2HUEhGIlxG+/2NSz2ppNPeg82iexaxus70NrGtmtmttaUxMJ4hSFZ74ToMF zsPzn24GFGBrCSZpTQb5kHp+cz+ZO6SvANtCAsFjJBY4Wyo1To8K5/sOzOy/WY2m tzvOwrFnGWlnmAPATopSN5eWYcPK60HFUkCrtj/bMLfI3b3ses787Z5YBegZRkGe g15zWuSp/B7rRQFagyYw7UtuCaKZdHlvAvBfOA+nIZP9wMX16v1vy41MHhMoD39z 4ZLjvq3xavdVGMNlFKTn8C/qQEMNS1WDXjI3IhU98+CTlpTirauSE1xccTIEwUWs okEvhSWGoc8HsgSMuNLI2OdlzQk3QkLGujd1QSB3KNA5Jwwjldnc/wB8gt3/T3W1 U4sGr4omig3hyv0+MHtnlmlzeQH+earq8aykTdqT1odLHLZwoBqFqhQFcuzG1puS VsL0KhR2X4BeNFz8rDtfjJ6qS/SH8nrUmXil2/peqwXWWwTDAkwVCSu+9OZ8PfjN ppcYaXyAm55OeDDx8GmC =vE53 -----END PGP SIGNATURE-----
On Wed, 9 Sep 2015 11:19:31 +0800 Weijie Gao <hackpascal@gmail.com> wrote: Hi, I'm working a bit on mainline support for the ATH79 and I would really like to see such patch making it there. I added this patch to my tree[1] with a few fixes to the log message. Would you mind submitting it to mainline? > Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by should be after the log message. > According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz > input clock as the REF_CLK instead of 5MHz. I have a similar problem on AR9132, the board I use (WR1043ND) have a 40MHz oscillator however the computation for the clocks assume a 5MHz input. Sadly I have no datasheet for the AR9132 so I can't fix the problem myself :/ > The correct CPU PLL calculation procedure is as follows: > CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. In the patch in my tree I replaced DIV with FB (for feedback i think, see [2]) as it then match with the register name used in the patch. Alban [1] https://github.com/AlbanBedel/linux/tree/ath79 [2] https://en.wikipedia.org/wiki/Phase-locked_loop#Feedback_path_and_optional_divider
diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch new file mode 100644 index 0000000..16d4621 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -25,7 +25,7 @@ + #include "common.h" + + #define AR71XX_BASE_FREQ 40000000 +-#define AR724X_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 40000000 + #define AR913X_BASE_FREQ 5000000 + + struct clk { +@@ -99,8 +99,8 @@ + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ref_rate; + +- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); +- freq *= div; ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; ++ freq /= div; + + cpu_rate = freq; +
Signed-off-by: Weijie Gao <hackpascal@gmail.com> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. --- ...MIPS-ath79-ar724x-clock-calculation-fixes.patch | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch