From patchwork Wed Sep 9 03:19:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weijie Gao X-Patchwork-Id: 515670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6883114012C for ; Wed, 9 Sep 2015 13:20:06 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=qrhSXe4q; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id E21F628AE10; Wed, 9 Sep 2015 05:18:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id E08A628BC2F for ; Wed, 9 Sep 2015 05:18:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 CL_IP_EQ_HELO_IP=-2 (check from: .gmail. - helo: .mail-pa0-f50.google. - helo-domain: .google.) FROM/MX_MATCHES_HELO(DOMAIN)=-2; rate: -8.5 Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Wed, 9 Sep 2015 05:18:47 +0200 (CEST) Received: by padhk3 with SMTP id hk3so57870538pad.3 for ; Tue, 08 Sep 2015 20:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Y5+ol1AQNYRr/lJ8CG1+Dcn/N82quFAaItI3GbhkR8g=; b=qrhSXe4qlRvUX2luDtuRNgMAPL74Egq0VomjPPiU7lfVdLLXgxx9gyUvRk1M9Oumje kAApStqqcbkatKNLHQ8fmTEgUYVpKdAmoe+T/ZtCsGp2P4hEhzFml7WT5k3g7RYiT5c7 e1CQLNatqFwl3D6mA0H2knx0sTn34bhaN51/IwXNTS+B0tfGWyUgSOUlY6GmtZLKzTQ7 b3arnmT5j9P3EGLjVj1sxmH2VMZpK1gaw8SHrpBgwe/A4EtgQJ0DAPlRsD6ypW6NTU4S hSxhy/OAIvT1f13q7Kx7XkQwCdtGq661LLxni6qxG8Mi1Kw7Fv8A1CgVW0kSXAzyf4Qa YTrg== X-Received: by 10.68.244.137 with SMTP id xg9mr65664034pbc.27.1441768790231; Tue, 08 Sep 2015 20:19:50 -0700 (PDT) Received: from localhost ([2605:f700:40:c00::ab48:b246]) by smtp.gmail.com with ESMTPSA id bh5sm5106018pbc.5.2015.09.08.20.19.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Sep 2015 20:19:49 -0700 (PDT) From: Weijie Gao To: openwrt-devel@lists.openwrt.org Date: Wed, 9 Sep 2015 11:19:31 +0800 Message-Id: <1441768771-18567-1-git-send-email-hackpascal@gmail.com> X-Mailer: git-send-email 2.1.4 Subject: [OpenWrt-Devel] [PATCH] ar71xx: fix ar724x clock calculation X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Signed-off-by: Weijie Gao According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. --- ...MIPS-ath79-ar724x-clock-calculation-fixes.patch | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch new file mode 100644 index 0000000..16d4621 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -25,7 +25,7 @@ + #include "common.h" + + #define AR71XX_BASE_FREQ 40000000 +-#define AR724X_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 40000000 + #define AR913X_BASE_FREQ 5000000 + + struct clk { +@@ -99,8 +99,8 @@ + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ref_rate; + +- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); +- freq *= div; ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; ++ freq /= div; + + cpu_rate = freq; +