diff mbox series

[v3,5/6] docs: platform: Add documentation for Renesas RZ/Five SoC

Message ID 20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com
State Superseded
Headers show
Series Add support for Renesas RZ/Five SoC | expand

Commit Message

Prabhakar Nov. 30, 2022, 10:08 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
* Updated doc with new build command

RFC->v2
* Updated doc
---
 docs/platform/platform.md       |   5 ++
 docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
 2 files changed, 150 insertions(+)
 create mode 100644 docs/platform/renesas-rzfive.md

Comments

Biju Das Dec. 1, 2022, 8:33 a.m. UTC | #1 
Hi Prabhakar,

Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> RZ/Five SoC
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Updated doc with new build command
> 
> RFC->v2
> * Updated doc
> ---
>  docs/platform/platform.md       |   5 ++
>  docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
>  2 files changed, 150 insertions(+)
>  create mode 100644 docs/platform/renesas-rzfive.md
> 
> diff --git a/docs/platform/platform.md b/docs/platform/platform.md index
> f291931..4504d87 100644
> --- a/docs/platform/platform.md
> +++ b/docs/platform/platform.md
> @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and
> hardware platforms:
>    processor based SOCs. More details on this platform can be found in
> the
>    file *[shakti_cclass.md]*.
> 
> +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> +(R9A07G043F) SoC
> +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> +platform can
> +  be found in the file *[renesas-rzfive.md]*.
> +
>  The code for these supported platforms can be used as example to
> implement  support for other platforms. The *platform/template*
> directory also provides  template files for implementing support for a
> new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to facilitate
> the implementation.
>  [spike.md]: spike.md
>  [fpga-openpiton.md]: fpga-openpiton.md
>  [shakti_cclass.md]: shakti_cclass.md
> +[renesas-rzfive.md]: renesas-rzfive.md
> diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> rzfive.md new file mode 100644 index 0000000..a900cc7
> --- /dev/null
> +++ b/docs/platform/renesas-rzfive.md
> @@ -0,0 +1,145 @@
> +Renesas RZ/Five SoC (R9A07G043F) Platform
> +=========================================
> +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> +AX45MP)
> +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> +- Gigabit Ethernet 2ch
> +- CAN interface (CAN-FD) 2ch
> +- USB 2.0 interface 2ch
> +- SD interface 2ch
> +- AD converter 2ch
> +making it ideal for applications such as entry-class social
> +infrastructure gateway control and industrial gateway control.
> +
> +To build platform specific library and firmwares, provide the
> +*PLATFORM=generic* parameter to the top level make command.
> +
> +Platform Options
> +----------------
> +
> +The Renesas RZ/Five platform does not have any platform-specific
> options.
> +
> +Building Renesas RZ/Five Platform
> +---------------------------------
> +
> +```
> +make PLATFORM=generic
> +```
> +
> +DTS Example: (RZ/Five AX45MP)
> +-----------------------------
> +
> +```
> +	compatible = "renesas,r9a07g043";
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <12000000>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "andestech,ax45mp", "riscv";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			status = "okay";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "riscv,sv39";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <0x40>;
> +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;

Missing clock names.

> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +			};
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		ranges;
> +
> +		scif0: serial@1004b800 {
> +			compatible = "renesas,scif-r9a07g043",
> +				     "renesas,scif-r9a07g044";
> +			reg = <0 0x1004b800 0 0x400>;
> +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";
> +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> +			clock-names = "fck";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> +			status = "disabled";
> +		};
> +
> +		cpg: clock-controller@11010000 {
> +			compatible = "renesas,r9a07g043-cpg";
> +			reg = <0 0x11010000 0 0x10000>;
> +			clocks = <&extal_clk>;
> +			clock-names = "extal";
> +			#clock-cells = <2>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <0>;
> +		};
> +
> +		sysc: system-controller@11020000 {
> +			compatible = "renesas,r9a07g043-sysc";
> +			reg = <0 0x11020000 0 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@11030000 {
> +			compatible = "renesas,r9a07g043-pinctrl";
> +			reg = <0 0x11030000 0 0x10000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			gpio-ranges = <&pinctrl 0 0 152>;
> +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
Missing reset names.

Cheers,
Biju
> +		};
> +
> +		plmt0: plmt0@110c0000 {
> +			compatible = "andestech,plmt0", "riscv,plmt0";
> +			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
> +			interrupts-extended = <&cpu0_intc 7>;
> +		};
> +
> +		plic: interrupt-controller@12c00000 {
> +			compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			riscv,ndev = <511>;
> +			interrupt-controller;
> +			reg = <0x0 0x12c00000 0 0x400000>;
> +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> +		};
> +
> +		plicsw: interrupt-controller@13000000 {
> +			compatible = "andestech,plicsw";
> +			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
> +			interrupts-extended = <&cpu0_intc 3>;
> +			interrupt-controller;
> +			#address-cells = <2>;
> +			#interrupt-cells = <2>;
> +		};
> +	};
> +```
> --
> 2.17.1
Biju Das Dec. 1, 2022, 8:41 a.m. UTC | #2 
Hi Prabhakar,

> Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Prabhakar,
> 
> Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > * Updated doc with new build command
> >
> > RFC->v2
> > * Updated doc
> > ---
> >  docs/platform/platform.md       |   5 ++
> >  docs/platform/renesas-rzfive.md | 145
> > ++++++++++++++++++++++++++++++++
> >  2 files changed, 150 insertions(+)
> >  create mode 100644 docs/platform/renesas-rzfive.md
> >
> > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > index
> > f291931..4504d87 100644
> > --- a/docs/platform/platform.md
> > +++ b/docs/platform/platform.md
> > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > and hardware platforms:
> >    processor based SOCs. More details on this platform can be found in
> > the
> >    file *[shakti_cclass.md]*.
> >
> > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > +(R9A07G043F) SoC
> > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > +platform can
> > +  be found in the file *[renesas-rzfive.md]*.
> > +
> >  The code for these supported platforms can be used as example to
> > implement  support for other platforms. The *platform/template*
> > directory also provides  template files for implementing support for a
> > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > facilitate the implementation.
> >  [spike.md]: spike.md
> >  [fpga-openpiton.md]: fpga-openpiton.md
> >  [shakti_cclass.md]: shakti_cclass.md
> > +[renesas-rzfive.md]: renesas-rzfive.md
> > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > rzfive.md new file mode 100644 index 0000000..a900cc7
> > --- /dev/null
> > +++ b/docs/platform/renesas-rzfive.md
> > @@ -0,0 +1,145 @@
> > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > +=========================================
> > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > +AX45MP)
> > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > +- Gigabit Ethernet 2ch
> > +- CAN interface (CAN-FD) 2ch
> > +- USB 2.0 interface 2ch
> > +- SD interface 2ch
> > +- AD converter 2ch

Only few interfaces. Maybe better add remaining one to avoid updating
this document every time.

Cheers,
Biju

> > +making it ideal for applications such as entry-class social
> > +infrastructure gateway control and industrial gateway control.
> > +
> > +To build platform specific library and firmwares, provide the
> > +*PLATFORM=generic* parameter to the top level make command.
> > +
> > +Platform Options
> > +----------------
> > +
> > +The Renesas RZ/Five platform does not have any platform-specific
> > options.
> > +
> > +Building Renesas RZ/Five Platform
> > +---------------------------------
> > +
> > +```
> > +make PLATFORM=generic
> > +```
> > +
> > +DTS Example: (RZ/Five AX45MP)
> > +-----------------------------
> > +
> > +```
> > +	compatible = "renesas,r9a07g043";
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <12000000>;
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "andestech,ax45mp", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0x0>;
> > +			status = "okay";
> > +			riscv,isa = "rv64imafdc";
> > +			mmu-type = "riscv,sv39";
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <0x40>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <0x40>;
> > +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> 
> Missing clock names.
> 
> > +			cpu0_intc: interrupt-controller {
> > +				#interrupt-cells = <1>;
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +			};
> > +		};
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		ranges;
> > +
> > +		scif0: serial@1004b800 {
> > +			compatible = "renesas,scif-r9a07g043",
> > +				     "renesas,scif-r9a07g044";
> > +			reg = <0 0x1004b800 0 0x400>;
> > +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "eri", "rxi", "txi",
> > +					  "bri", "dri", "tei";
> > +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > +			clock-names = "fck";
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > +			status = "disabled";
> > +		};
> > +
> > +		cpg: clock-controller@11010000 {
> > +			compatible = "renesas,r9a07g043-cpg";
> > +			reg = <0 0x11010000 0 0x10000>;
> > +			clocks = <&extal_clk>;
> > +			clock-names = "extal";
> > +			#clock-cells = <2>;
> > +			#reset-cells = <1>;
> > +			#power-domain-cells = <0>;
> > +		};
> > +
> > +		sysc: system-controller@11020000 {
> > +			compatible = "renesas,r9a07g043-sysc";
> > +			reg = <0 0x11020000 0 0x10000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		pinctrl: pinctrl@11030000 {
> > +			compatible = "renesas,r9a07g043-pinctrl";
> > +			reg = <0 0x11030000 0 0x10000>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			#interrupt-cells = <2>;
> > +			interrupt-controller;
> > +			gpio-ranges = <&pinctrl 0 0 152>;
> > +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> > +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> Missing reset names.
> 
> Cheers,
> Biju
> > +		};
> > +
> > +		plmt0: plmt0@110c0000 {
> > +			compatible = "andestech,plmt0", "riscv,plmt0";
> > +			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
> > +			interrupts-extended = <&cpu0_intc 7>;
> > +		};
> > +
> > +		plic: interrupt-controller@12c00000 {
> > +			compatible = "renesas,r9a07g043-plic",
> > "andestech,nceplic100";
> > +			#interrupt-cells = <2>;
> > +			#address-cells = <0>;
> > +			riscv,ndev = <511>;
> > +			interrupt-controller;
> > +			reg = <0x0 0x12c00000 0 0x400000>;
> > +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> > +		};
> > +
> > +		plicsw: interrupt-controller@13000000 {
> > +			compatible = "andestech,plicsw";
> > +			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
> > +			interrupts-extended = <&cpu0_intc 3>;
> > +			interrupt-controller;
> > +			#address-cells = <2>;
> > +			#interrupt-cells = <2>;
> > +		};
> > +	};
> > +```
> > --
> > 2.17.1
Prabhakar Dec. 1, 2022, 9:09 a.m. UTC | #3 
Hi Biju,

Thank you for the review.

On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > * Updated doc with new build command
> >
> > RFC->v2
> > * Updated doc
> > ---
> >  docs/platform/platform.md       |   5 ++
> >  docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
> >  2 files changed, 150 insertions(+)
> >  create mode 100644 docs/platform/renesas-rzfive.md
> >
> > diff --git a/docs/platform/platform.md b/docs/platform/platform.md index
> > f291931..4504d87 100644
> > --- a/docs/platform/platform.md
> > +++ b/docs/platform/platform.md
> > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and
> > hardware platforms:
> >    processor based SOCs. More details on this platform can be found in
> > the
> >    file *[shakti_cclass.md]*.
> >
> > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > +(R9A07G043F) SoC
> > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > +platform can
> > +  be found in the file *[renesas-rzfive.md]*.
> > +
> >  The code for these supported platforms can be used as example to
> > implement  support for other platforms. The *platform/template*
> > directory also provides  template files for implementing support for a
> > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to facilitate
> > the implementation.
> >  [spike.md]: spike.md
> >  [fpga-openpiton.md]: fpga-openpiton.md
> >  [shakti_cclass.md]: shakti_cclass.md
> > +[renesas-rzfive.md]: renesas-rzfive.md
> > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > rzfive.md new file mode 100644 index 0000000..a900cc7
> > --- /dev/null
> > +++ b/docs/platform/renesas-rzfive.md
> > @@ -0,0 +1,145 @@
> > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > +=========================================
> > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > +AX45MP)
> > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > +- Gigabit Ethernet 2ch
> > +- CAN interface (CAN-FD) 2ch
> > +- USB 2.0 interface 2ch
> > +- SD interface 2ch
> > +- AD converter 2ch
> > +making it ideal for applications such as entry-class social
> > +infrastructure gateway control and industrial gateway control.
> > +
> > +To build platform specific library and firmwares, provide the
> > +*PLATFORM=generic* parameter to the top level make command.
> > +
> > +Platform Options
> > +----------------
> > +
> > +The Renesas RZ/Five platform does not have any platform-specific
> > options.
> > +
> > +Building Renesas RZ/Five Platform
> > +---------------------------------
> > +
> > +```
> > +make PLATFORM=generic
> > +```
> > +
> > +DTS Example: (RZ/Five AX45MP)
> > +-----------------------------
> > +
> > +```
> > +     compatible = "renesas,r9a07g043";
> > +
> > +     cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             timebase-frequency = <12000000>;
> > +
> > +             cpu0: cpu@0 {
> > +                     compatible = "andestech,ax45mp", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <0x0>;
> > +                     status = "okay";
> > +                     riscv,isa = "rv64imafdc";
> > +                     mmu-type = "riscv,sv39";
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-line-size = <0x40>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-line-size = <0x40>;
> > +                     clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > +                              <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
>
> Missing clock names.
>
> > +                     cpu0_intc: interrupt-controller {
> > +                             #interrupt-cells = <1>;
> > +                             compatible = "riscv,cpu-intc";
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +     };
> > +
> > +     soc {
> > +             compatible = "simple-bus";
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             ranges;
> > +
> > +             scif0: serial@1004b800 {
> > +                     compatible = "renesas,scif-r9a07g043",
> > +                                  "renesas,scif-r9a07g044";
> > +                     reg = <0 0x1004b800 0 0x400>;
> > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > +                     interrupt-names = "eri", "rxi", "txi",
> > +                                       "bri", "dri", "tei";
> > +                     clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > +                     clock-names = "fck";
> > +                     power-domains = <&cpg>;
> > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             cpg: clock-controller@11010000 {
> > +                     compatible = "renesas,r9a07g043-cpg";
> > +                     reg = <0 0x11010000 0 0x10000>;
> > +                     clocks = <&extal_clk>;
> > +                     clock-names = "extal";
> > +                     #clock-cells = <2>;
> > +                     #reset-cells = <1>;
> > +                     #power-domain-cells = <0>;
> > +             };
> > +
> > +             sysc: system-controller@11020000 {
> > +                     compatible = "renesas,r9a07g043-sysc";
> > +                     reg = <0 0x11020000 0 0x10000>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             pinctrl: pinctrl@11030000 {
> > +                     compatible = "renesas,r9a07g043-pinctrl";
> > +                     reg = <0 0x11030000 0 0x10000>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     #interrupt-cells = <2>;
> > +                     interrupt-controller;
> > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > +                     power-domains = <&cpg>;
> > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> Missing reset names.
>
Binding doesn't have reset names.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml?h=next-20221201

Cheers,
Prabhakar
Prabhakar Dec. 1, 2022, 9:12 a.m. UTC | #4 
Hi Biju,

On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Prabhakar,
> >
> > Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > > RZ/Five SoC
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> > SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > > * Updated doc with new build command
> > >
> > > RFC->v2
> > > * Updated doc
> > > ---
> > >  docs/platform/platform.md       |   5 ++
> > >  docs/platform/renesas-rzfive.md | 145
> > > ++++++++++++++++++++++++++++++++
> > >  2 files changed, 150 insertions(+)
> > >  create mode 100644 docs/platform/renesas-rzfive.md
> > >
> > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > index
> > > f291931..4504d87 100644
> > > --- a/docs/platform/platform.md
> > > +++ b/docs/platform/platform.md
> > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > and hardware platforms:
> > >    processor based SOCs. More details on this platform can be found in
> > > the
> > >    file *[shakti_cclass.md]*.
> > >
> > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > +(R9A07G043F) SoC
> > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > +platform can
> > > +  be found in the file *[renesas-rzfive.md]*.
> > > +
> > >  The code for these supported platforms can be used as example to
> > > implement  support for other platforms. The *platform/template*
> > > directory also provides  template files for implementing support for a
> > > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > facilitate the implementation.
> > >  [spike.md]: spike.md
> > >  [fpga-openpiton.md]: fpga-openpiton.md
> > >  [shakti_cclass.md]: shakti_cclass.md
> > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > > rzfive.md new file mode 100644 index 0000000..a900cc7
> > > --- /dev/null
> > > +++ b/docs/platform/renesas-rzfive.md
> > > @@ -0,0 +1,145 @@
> > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > +=========================================
> > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > +AX45MP)
> > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > +- Gigabit Ethernet 2ch
> > > +- CAN interface (CAN-FD) 2ch
> > > +- USB 2.0 interface 2ch
> > > +- SD interface 2ch
> > > +- AD converter 2ch
>
> Only few interfaces. Maybe better add remaining one to avoid updating
> this document every time.
>
The above list is from the Renesas website [0] (Features tab)

Can you please list out which all you want me to add?

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet#overview

Cheers,
Prabhakar
Biju Das Dec. 1, 2022, 9:13 a.m. UTC | #5 
Hi Prabhakar,

> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > > * Updated doc with new build command
> > >
> > > RFC->v2
> > > * Updated doc
> > > ---
> > >  docs/platform/platform.md       |   5 ++
> > >  docs/platform/renesas-rzfive.md | 145
> > > ++++++++++++++++++++++++++++++++
> > >  2 files changed, 150 insertions(+)
> > >  create mode 100644 docs/platform/renesas-rzfive.md
> > >
> > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > index
> > > f291931..4504d87 100644
> > > --- a/docs/platform/platform.md
> > > +++ b/docs/platform/platform.md
> > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > and hardware platforms:
> > >    processor based SOCs. More details on this platform can be found
> > > in the
> > >    file *[shakti_cclass.md]*.
> > >
> > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > +(R9A07G043F) SoC
> > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > +platform can
> > > +  be found in the file *[renesas-rzfive.md]*.
> > > +
> > >  The code for these supported platforms can be used as example to
> > > implement  support for other platforms. The *platform/template*
> > > directory also provides  template files for implementing support for
> > > a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > facilitate the implementation.
> > >  [spike.md]: spike.md
> > >  [fpga-openpiton.md]: fpga-openpiton.md
> > >  [shakti_cclass.md]: shakti_cclass.md
> > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > diff --git a/docs/platform/renesas-rzfive.md
> > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > 0000000..a900cc7
> > > --- /dev/null
> > > +++ b/docs/platform/renesas-rzfive.md
> > > @@ -0,0 +1,145 @@
> > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > +=========================================
> > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > +AX45MP)
> > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > +- Gigabit Ethernet 2ch
> > > +- CAN interface (CAN-FD) 2ch
> > > +- USB 2.0 interface 2ch
> > > +- SD interface 2ch
> > > +- AD converter 2ch
> > > +making it ideal for applications such as entry-class social
> > > +infrastructure gateway control and industrial gateway control.
> > > +
> > > +To build platform specific library and firmwares, provide the
> > > +*PLATFORM=generic* parameter to the top level make command.
> > > +
> > > +Platform Options
> > > +----------------
> > > +
> > > +The Renesas RZ/Five platform does not have any platform-specific
> > > options.
> > > +
> > > +Building Renesas RZ/Five Platform
> > > +---------------------------------
> > > +
> > > +```
> > > +make PLATFORM=generic
> > > +```
> > > +
> > > +DTS Example: (RZ/Five AX45MP)
> > > +-----------------------------
> > > +
> > > +```
> > > +     compatible = "renesas,r9a07g043";
> > > +
> > > +     cpus {
> > > +             #address-cells = <1>;
> > > +             #size-cells = <0>;
> > > +             timebase-frequency = <12000000>;
> > > +
> > > +             cpu0: cpu@0 {
> > > +                     compatible = "andestech,ax45mp", "riscv";
> > > +                     device_type = "cpu";
> > > +                     reg = <0x0>;
> > > +                     status = "okay";
> > > +                     riscv,isa = "rv64imafdc";
> > > +                     mmu-type = "riscv,sv39";
> > > +                     i-cache-size = <0x8000>;
> > > +                     i-cache-line-size = <0x40>;
> > > +                     d-cache-size = <0x8000>;
> > > +                     d-cache-line-size = <0x40>;
> > > +                     clocks = <&cpg CPG_CORE
> R9A07G043_AX45MP_CORE0_CLK>,
> > > +                              <&cpg CPG_CORE
> > > + R9A07G043_AX45MP_ACLK>;
> >
> > Missing clock names.
> >
> > > +                     cpu0_intc: interrupt-controller {
> > > +                             #interrupt-cells = <1>;
> > > +                             compatible = "riscv,cpu-intc";
> > > +                             interrupt-controller;
> > > +                     };
> > > +             };
> > > +     };
> > > +
> > > +     soc {
> > > +             compatible = "simple-bus";
> > > +             #address-cells = <1>;
> > > +             #size-cells = <0>;
> > > +             ranges;
> > > +
> > > +             scif0: serial@1004b800 {
> > > +                     compatible = "renesas,scif-r9a07g043",
> > > +                                  "renesas,scif-r9a07g044";
> > > +                     reg = <0 0x1004b800 0 0x400>;
> > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > +                     interrupt-names = "eri", "rxi", "txi",
> > > +                                       "bri", "dri", "tei";
> > > +                     clocks = <&cpg CPG_MOD
> R9A07G043_SCIF0_CLK_PCK>;
> > > +                     clock-names = "fck";
> > > +                     power-domains = <&cpg>;
> > > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > > +             cpg: clock-controller@11010000 {
> > > +                     compatible = "renesas,r9a07g043-cpg";
> > > +                     reg = <0 0x11010000 0 0x10000>;
> > > +                     clocks = <&extal_clk>;
> > > +                     clock-names = "extal";
> > > +                     #clock-cells = <2>;
> > > +                     #reset-cells = <1>;
> > > +                     #power-domain-cells = <0>;
> > > +             };
> > > +
> > > +             sysc: system-controller@11020000 {
> > > +                     compatible = "renesas,r9a07g043-sysc";
> > > +                     reg = <0 0x11020000 0 0x10000>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > > +             pinctrl: pinctrl@11030000 {
> > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > +                     reg = <0 0x11030000 0 0x10000>;
> > > +                     gpio-controller;
> > > +                     #gpio-cells = <2>;
> > > +                     #interrupt-cells = <2>;
> > > +                     interrupt-controller;
> > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > > +                     power-domains = <&cpg>;
> > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > Missing reset names.
> >
> Binding doesn't have reset names.

Maybe add here and upstream the same patch to Linux.

Cheers,
Biju
Prabhakar Dec. 1, 2022, 9:19 a.m. UTC | #6 
Hi Biju,

On Thu, Dec 1, 2022 at 9:13 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v2->v3
> > > > * Updated doc with new build command
> > > >
> > > > RFC->v2
> > > > * Updated doc
> > > > ---
> > > >  docs/platform/platform.md       |   5 ++
> > > >  docs/platform/renesas-rzfive.md | 145
> > > > ++++++++++++++++++++++++++++++++
> > > >  2 files changed, 150 insertions(+)
> > > >  create mode 100644 docs/platform/renesas-rzfive.md
> > > >
> > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > index
> > > > f291931..4504d87 100644
> > > > --- a/docs/platform/platform.md
> > > > +++ b/docs/platform/platform.md
> > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > > and hardware platforms:
> > > >    processor based SOCs. More details on this platform can be found
> > > > in the
> > > >    file *[shakti_cclass.md]*.
> > > >
> > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > +(R9A07G043F) SoC
> > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > > +platform can
> > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > +
> > > >  The code for these supported platforms can be used as example to
> > > > implement  support for other platforms. The *platform/template*
> > > > directory also provides  template files for implementing support for
> > > > a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > > facilitate the implementation.
> > > >  [spike.md]: spike.md
> > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > 0000000..a900cc7
> > > > --- /dev/null
> > > > +++ b/docs/platform/renesas-rzfive.md
> > > > @@ -0,0 +1,145 @@
> > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > +=========================================
> > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > > +AX45MP)
> > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > > +- Gigabit Ethernet 2ch
> > > > +- CAN interface (CAN-FD) 2ch
> > > > +- USB 2.0 interface 2ch
> > > > +- SD interface 2ch
> > > > +- AD converter 2ch
> > > > +making it ideal for applications such as entry-class social
> > > > +infrastructure gateway control and industrial gateway control.
> > > > +
> > > > +To build platform specific library and firmwares, provide the
> > > > +*PLATFORM=generic* parameter to the top level make command.
> > > > +
> > > > +Platform Options
> > > > +----------------
> > > > +
> > > > +The Renesas RZ/Five platform does not have any platform-specific
> > > > options.
> > > > +
> > > > +Building Renesas RZ/Five Platform
> > > > +---------------------------------
> > > > +
> > > > +```
> > > > +make PLATFORM=generic
> > > > +```
> > > > +
> > > > +DTS Example: (RZ/Five AX45MP)
> > > > +-----------------------------
> > > > +
> > > > +```
> > > > +     compatible = "renesas,r9a07g043";
> > > > +
> > > > +     cpus {
> > > > +             #address-cells = <1>;
> > > > +             #size-cells = <0>;
> > > > +             timebase-frequency = <12000000>;
> > > > +
> > > > +             cpu0: cpu@0 {
> > > > +                     compatible = "andestech,ax45mp", "riscv";
> > > > +                     device_type = "cpu";
> > > > +                     reg = <0x0>;
> > > > +                     status = "okay";
> > > > +                     riscv,isa = "rv64imafdc";
> > > > +                     mmu-type = "riscv,sv39";
> > > > +                     i-cache-size = <0x8000>;
> > > > +                     i-cache-line-size = <0x40>;
> > > > +                     d-cache-size = <0x8000>;
> > > > +                     d-cache-line-size = <0x40>;
> > > > +                     clocks = <&cpg CPG_CORE
> > R9A07G043_AX45MP_CORE0_CLK>,
> > > > +                              <&cpg CPG_CORE
> > > > + R9A07G043_AX45MP_ACLK>;
> > >
> > > Missing clock names.
> > >
> > > > +                     cpu0_intc: interrupt-controller {
> > > > +                             #interrupt-cells = <1>;
> > > > +                             compatible = "riscv,cpu-intc";
> > > > +                             interrupt-controller;
> > > > +                     };
> > > > +             };
> > > > +     };
> > > > +
> > > > +     soc {
> > > > +             compatible = "simple-bus";
> > > > +             #address-cells = <1>;
> > > > +             #size-cells = <0>;
> > > > +             ranges;
> > > > +
> > > > +             scif0: serial@1004b800 {
> > > > +                     compatible = "renesas,scif-r9a07g043",
> > > > +                                  "renesas,scif-r9a07g044";
> > > > +                     reg = <0 0x1004b800 0 0x400>;
> > > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > > +                     interrupt-names = "eri", "rxi", "txi",
> > > > +                                       "bri", "dri", "tei";
> > > > +                     clocks = <&cpg CPG_MOD
> > R9A07G043_SCIF0_CLK_PCK>;
> > > > +                     clock-names = "fck";
> > > > +                     power-domains = <&cpg>;
> > > > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > > +             cpg: clock-controller@11010000 {
> > > > +                     compatible = "renesas,r9a07g043-cpg";
> > > > +                     reg = <0 0x11010000 0 0x10000>;
> > > > +                     clocks = <&extal_clk>;
> > > > +                     clock-names = "extal";
> > > > +                     #clock-cells = <2>;
> > > > +                     #reset-cells = <1>;
> > > > +                     #power-domain-cells = <0>;
> > > > +             };
> > > > +
> > > > +             sysc: system-controller@11020000 {
> > > > +                     compatible = "renesas,r9a07g043-sysc";
> > > > +                     reg = <0 0x11020000 0 0x10000>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > > +             pinctrl: pinctrl@11030000 {
> > > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > > +                     reg = <0 0x11030000 0 0x10000>;
> > > > +                     gpio-controller;
> > > > +                     #gpio-cells = <2>;
> > > > +                     #interrupt-cells = <2>;
> > > > +                     interrupt-controller;
> > > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > > > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > > Missing reset names.
> > >
> > Binding doesn't have reset names.
>
> Maybe add here and upstream the same patch to Linux.
>
OK, I'll only add here once it's accepted in upstream Linux (as what
if it's not accepted there I dont want to misguide).

Cheers,
Prabhakar
Biju Das Dec. 1, 2022, 9:21 a.m. UTC | #7 
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 01 December 2022 09:20
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Anup Patel <anup@brainfault.org>; Atish Patra
> <atishp@atishpatra.org>; opensbi@lists.infradead.org; Yu Chien Peter Lin
> <peterlin@andestech.com>; Bin Meng <bmeng.cn@gmail.com>; Andrew Jones
> <ajones@ventanamicro.com>; Chris Paterson <Chris.Paterson2@renesas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> On Thu, Dec 1, 2022 at 9:13 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > Hi Biju,
> > >
> > > Thank you for the review.
> > >
> > > On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Prabhakar Mahadev Lad
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > > Renesas RZ/Five SoC
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > This patch adds documentation to build Renesas RZ/Five
> > > > > (R9A07G043F)
> > > SoC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v2->v3
> > > > > * Updated doc with new build command
> > > > >
> > > > > RFC->v2
> > > > > * Updated doc
> > > > > ---
> > > > >  docs/platform/platform.md       |   5 ++
> > > > >  docs/platform/renesas-rzfive.md | 145
> > > > > ++++++++++++++++++++++++++++++++
> > > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > > docs/platform/renesas-rzfive.md
> > > > >
> > > > > diff --git a/docs/platform/platform.md
> > > > > b/docs/platform/platform.md index
> > > > > f291931..4504d87 100644
> > > > > --- a/docs/platform/platform.md
> > > > > +++ b/docs/platform/platform.md
> > > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > > virtual and hardware platforms:
> > > > >    processor based SOCs. More details on this platform can be
> > > > > found in the
> > > > >    file *[shakti_cclass.md]*.
> > > > >
> > > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > > +(R9A07G043F) SoC
> > > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > > +this platform can
> > > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > > +
> > > > >  The code for these supported platforms can be used as example
> > > > > to implement  support for other platforms. The
> > > > > *platform/template* directory also provides  template files for
> > > > > implementing support for a new platform. The *objects.mk*, @@
> > > > > -54,3 +58,4 @@ comments to facilitate the implementation.
> > > > >  [spike.md]: spike.md
> > > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > > 0000000..a900cc7
> > > > > --- /dev/null
> > > > > +++ b/docs/platform/renesas-rzfive.md
> > > > > @@ -0,0 +1,145 @@
> > > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > > +=========================================
> > > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > > +(Andes
> > > > > +AX45MP)
> > > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> include:
> > > > > +- Gigabit Ethernet 2ch
> > > > > +- CAN interface (CAN-FD) 2ch
> > > > > +- USB 2.0 interface 2ch
> > > > > +- SD interface 2ch
> > > > > +- AD converter 2ch
> > > > > +making it ideal for applications such as entry-class social
> > > > > +infrastructure gateway control and industrial gateway control.
> > > > > +
> > > > > +To build platform specific library and firmwares, provide the
> > > > > +*PLATFORM=generic* parameter to the top level make command.
> > > > > +
> > > > > +Platform Options
> > > > > +----------------
> > > > > +
> > > > > +The Renesas RZ/Five platform does not have any
> > > > > +platform-specific
> > > > > options.
> > > > > +
> > > > > +Building Renesas RZ/Five Platform
> > > > > +---------------------------------
> > > > > +
> > > > > +```
> > > > > +make PLATFORM=generic
> > > > > +```
> > > > > +
> > > > > +DTS Example: (RZ/Five AX45MP)
> > > > > +-----------------------------
> > > > > +
> > > > > +```
> > > > > +     compatible = "renesas,r9a07g043";
> > > > > +
> > > > > +     cpus {
> > > > > +             #address-cells = <1>;
> > > > > +             #size-cells = <0>;
> > > > > +             timebase-frequency = <12000000>;
> > > > > +
> > > > > +             cpu0: cpu@0 {
> > > > > +                     compatible = "andestech,ax45mp", "riscv";
> > > > > +                     device_type = "cpu";
> > > > > +                     reg = <0x0>;
> > > > > +                     status = "okay";
> > > > > +                     riscv,isa = "rv64imafdc";
> > > > > +                     mmu-type = "riscv,sv39";
> > > > > +                     i-cache-size = <0x8000>;
> > > > > +                     i-cache-line-size = <0x40>;
> > > > > +                     d-cache-size = <0x8000>;
> > > > > +                     d-cache-line-size = <0x40>;
> > > > > +                     clocks = <&cpg CPG_CORE
> > > R9A07G043_AX45MP_CORE0_CLK>,
> > > > > +                              <&cpg CPG_CORE
> > > > > + R9A07G043_AX45MP_ACLK>;
> > > >
> > > > Missing clock names.
> > > >
> > > > > +                     cpu0_intc: interrupt-controller {
> > > > > +                             #interrupt-cells = <1>;
> > > > > +                             compatible = "riscv,cpu-intc";
> > > > > +                             interrupt-controller;
> > > > > +                     };
> > > > > +             };
> > > > > +     };
> > > > > +
> > > > > +     soc {
> > > > > +             compatible = "simple-bus";
> > > > > +             #address-cells = <1>;
> > > > > +             #size-cells = <0>;
> > > > > +             ranges;
> > > > > +
> > > > > +             scif0: serial@1004b800 {
> > > > > +                     compatible = "renesas,scif-r9a07g043",
> > > > > +                                  "renesas,scif-r9a07g044";
> > > > > +                     reg = <0 0x1004b800 0 0x400>;
> > > > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                     interrupt-names = "eri", "rxi", "txi",
> > > > > +                                       "bri", "dri", "tei";
> > > > > +                     clocks = <&cpg CPG_MOD
> > > R9A07G043_SCIF0_CLK_PCK>;
> > > > > +                     clock-names = "fck";
> > > > > +                     power-domains = <&cpg>;
> > > > > +                     resets = <&cpg
> R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > > > +                     status = "disabled";
> > > > > +             };
> > > > > +
> > > > > +             cpg: clock-controller@11010000 {
> > > > > +                     compatible = "renesas,r9a07g043-cpg";
> > > > > +                     reg = <0 0x11010000 0 0x10000>;
> > > > > +                     clocks = <&extal_clk>;
> > > > > +                     clock-names = "extal";
> > > > > +                     #clock-cells = <2>;
> > > > > +                     #reset-cells = <1>;
> > > > > +                     #power-domain-cells = <0>;
> > > > > +             };
> > > > > +
> > > > > +             sysc: system-controller@11020000 {
> > > > > +                     compatible = "renesas,r9a07g043-sysc";
> > > > > +                     reg = <0 0x11020000 0 0x10000>;
> > > > > +                     status = "disabled";
> > > > > +             };
> > > > > +
> > > > > +             pinctrl: pinctrl@11030000 {
> > > > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > > > +                     reg = <0 0x11030000 0 0x10000>;
> > > > > +                     gpio-controller;
> > > > > +                     #gpio-cells = <2>;
> > > > > +                     #interrupt-cells = <2>;
> > > > > +                     interrupt-controller;
> > > > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > > > +                     clocks = <&cpg CPG_MOD
> R9A07G043_GPIO_HCLK>;
> > > > > +                     power-domains = <&cpg>;
> > > > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > > > +                              <&cpg
> R9A07G043_GPIO_PORT_RESETN>,
> > > > > +                              <&cpg
> > > > > + R9A07G043_GPIO_SPARE_RESETN>;
> > > > Missing reset names.
> > > >
> > > Binding doesn't have reset names.
> >
> > Maybe add here and upstream the same patch to Linux.
> >
> OK, I'll only add here once it's accepted in upstream Linux (as what if
> it's not accepted there I dont want to misguide).

OK for me.

Cheers,
Biju
Biju Das Dec. 1, 2022, 9:38 a.m. UTC | #8 
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 01 December 2022 09:12
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Anup Patel <anup@brainfault.org>; Atish Patra
> <atishp@atishpatra.org>; opensbi@lists.infradead.org; Yu Chien Peter Lin
> <peterlin@andestech.com>; Bin Meng <bmeng.cn@gmail.com>; Andrew Jones
> <ajones@ventanamicro.com>; Chris Paterson <Chris.Paterson2@renesas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > Hi Prabhakar,
> > >
> > > Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > This patch adds documentation to build Renesas RZ/Five
> > > > (R9A07G043F)
> > > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v2->v3
> > > > * Updated doc with new build command
> > > >
> > > > RFC->v2
> > > > * Updated doc
> > > > ---
> > > >  docs/platform/platform.md       |   5 ++
> > > >  docs/platform/renesas-rzfive.md | 145
> > > > ++++++++++++++++++++++++++++++++
> > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > docs/platform/renesas-rzfive.md
> > > >
> > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > index
> > > > f291931..4504d87 100644
> > > > --- a/docs/platform/platform.md
> > > > +++ b/docs/platform/platform.md
> > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > virtual and hardware platforms:
> > > >    processor based SOCs. More details on this platform can be
> > > > found in the
> > > >    file *[shakti_cclass.md]*.
> > > >
> > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > +(R9A07G043F) SoC
> > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > +this platform can
> > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > +
> > > >  The code for these supported platforms can be used as example to
> > > > implement  support for other platforms. The *platform/template*
> > > > directory also provides  template files for implementing support
> > > > for a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments
> > > > to facilitate the implementation.
> > > >  [spike.md]: spike.md
> > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > 0000000..a900cc7
> > > > --- /dev/null
> > > > +++ b/docs/platform/renesas-rzfive.md
> > > > @@ -0,0 +1,145 @@
> > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > +=========================================
> > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > +(Andes
> > > > +AX45MP)
> > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> include:
> > > > +- Gigabit Ethernet 2ch
> > > > +- CAN interface (CAN-FD) 2ch
> > > > +- USB 2.0 interface 2ch
> > > > +- SD interface 2ch
> > > > +- AD converter 2ch
> >
> > Only few interfaces. Maybe better add remaining one to avoid updating
> > this document every time.
> >
> The above list is from the Renesas website [0] (Features tab)
> 
> Can you please list out which all you want me to add?
> 

Maybe you add all 

− Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits,
− USB2.0 host / function interface,
− Gigabit Ethernet interface,
− SD card host interface,
− CAN interface,
− Sound interface
- SPI Multi I/O Bus Controller
- Multi-function Timer Pulse Unit 3(MTU3a)
- Port Output Enable 3(POE3)
- Watchdog Timer(WDT)
- General Timer(GTM)
- I2C Bus Interface (I2C)
- Serial Communication Interface with FIFO (SCIFA)
- Serial Communication Interface(SCI)
- Renesas Serial Peripheral Interface (RSPI)

or subset What is going to be supported in open SBI
like

1)CPU
2)Memory
3)IRQ
4)SCIF
5)SPI Multi I/O Bus Controller ( for QSPI boot)
6)SDHI(for eMMC boot)
7)GTM for Secure OS
8)WDT

Cheers,
Biju
Prabhakar Dec. 1, 2022, 10:48 a.m. UTC | #9 
On Thu, Dec 1, 2022 at 9:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 01 December 2022 09:12
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Anup Patel <anup@brainfault.org>; Atish Patra
> > <atishp@atishpatra.org>; opensbi@lists.infradead.org; Yu Chien Peter Lin
> > <peterlin@andestech.com>; Bin Meng <bmeng.cn@gmail.com>; Andrew Jones
> > <ajones@ventanamicro.com>; Chris Paterson <Chris.Paterson2@renesas.com>;
> > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Biju,
> >
> > On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Prabhakar Mahadev Lad
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > > Renesas RZ/Five SoC
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > This patch adds documentation to build Renesas RZ/Five
> > > > > (R9A07G043F)
> > > > SoC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v2->v3
> > > > > * Updated doc with new build command
> > > > >
> > > > > RFC->v2
> > > > > * Updated doc
> > > > > ---
> > > > >  docs/platform/platform.md       |   5 ++
> > > > >  docs/platform/renesas-rzfive.md | 145
> > > > > ++++++++++++++++++++++++++++++++
> > > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > > docs/platform/renesas-rzfive.md
> > > > >
> > > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > > index
> > > > > f291931..4504d87 100644
> > > > > --- a/docs/platform/platform.md
> > > > > +++ b/docs/platform/platform.md
> > > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > > virtual and hardware platforms:
> > > > >    processor based SOCs. More details on this platform can be
> > > > > found in the
> > > > >    file *[shakti_cclass.md]*.
> > > > >
> > > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > > +(R9A07G043F) SoC
> > > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > > +this platform can
> > > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > > +
> > > > >  The code for these supported platforms can be used as example to
> > > > > implement  support for other platforms. The *platform/template*
> > > > > directory also provides  template files for implementing support
> > > > > for a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments
> > > > > to facilitate the implementation.
> > > > >  [spike.md]: spike.md
> > > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > > 0000000..a900cc7
> > > > > --- /dev/null
> > > > > +++ b/docs/platform/renesas-rzfive.md
> > > > > @@ -0,0 +1,145 @@
> > > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > > +=========================================
> > > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > > +(Andes
> > > > > +AX45MP)
> > > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> > include:
> > > > > +- Gigabit Ethernet 2ch
> > > > > +- CAN interface (CAN-FD) 2ch
> > > > > +- USB 2.0 interface 2ch
> > > > > +- SD interface 2ch
> > > > > +- AD converter 2ch
> > >
> > > Only few interfaces. Maybe better add remaining one to avoid updating
> > > this document every time.
> > >
> > The above list is from the Renesas website [0] (Features tab)
> >
> > Can you please list out which all you want me to add?
> >
>
> Maybe you add all
>
> − Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits,
> − USB2.0 host / function interface,
> − Gigabit Ethernet interface,
> − SD card host interface,
> − CAN interface,
> − Sound interface
> - SPI Multi I/O Bus Controller
> - Multi-function Timer Pulse Unit 3(MTU3a)
> - Port Output Enable 3(POE3)
> - Watchdog Timer(WDT)
> - General Timer(GTM)
> - I2C Bus Interface (I2C)
> - Serial Communication Interface with FIFO (SCIFA)
> - Serial Communication Interface(SCI)
> - Renesas Serial Peripheral Interface (RSPI)
>
OK I will add the above.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index f291931..4504d87 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,6 +39,10 @@  OpenSBI currently supports the following virtual and hardware platforms:
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
 
+* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
+  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
+  be found in the file *[renesas-rzfive.md]*.
+
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *objects.mk*,
@@ -54,3 +58,4 @@  comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
+[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
new file mode 100644
index 0000000..a900cc7
--- /dev/null
+++ b/docs/platform/renesas-rzfive.md
@@ -0,0 +1,145 @@ 
+Renesas RZ/Five SoC (R9A07G043F) Platform
+=========================================
+The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
+1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
+- Gigabit Ethernet 2ch
+- CAN interface (CAN-FD) 2ch
+- USB 2.0 interface 2ch
+- SD interface 2ch
+- AD converter 2ch
+making it ideal for applications such as entry-class social infrastructure
+gateway control and industrial gateway control.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=generic* parameter to the top level make command.
+
+Platform Options
+----------------
+
+The Renesas RZ/Five platform does not have any platform-specific options.
+
+Building Renesas RZ/Five Platform
+---------------------------------
+
+```
+make PLATFORM=generic
+```
+
+DTS Example: (RZ/Five AX45MP)
+-----------------------------
+
+```
+	compatible = "renesas,r9a07g043";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <12000000>;
+
+		cpu0: cpu@0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ranges;
+
+		scif0: serial@1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller@11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plmt0: plmt0@110c0000 {
+			compatible = "andestech,plmt0", "riscv,plmt0";
+			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
+			interrupts-extended = <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller@12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <511>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+
+		plicsw: interrupt-controller@13000000 {
+			compatible = "andestech,plicsw";
+			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
+			interrupts-extended = <&cpu0_intc 3>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+		};
+	};
+```