| Message ID | 20200319122737.3063291-1-thierry.reding@gmail.com |
|---|---|
| Headers | show |
| Series | pinctrl: tegra: Support SFIO/GPIO programming | expand |
On 3/19/2020 5:57 PM, Thierry Reding wrote: > External email: Use caution opening links or attachments > > > From: Thierry Reding <treding@nvidia.com> > > Hi, > > NVIDIA Tegra186 and later have a bit in the pin controller that defines > whether a pin is used in special function (SFIO) mode or in general > purpose (GPIO) mode. On early Tegra SoC generations, this bit was part > of the GPIO controller. > > The pin configuration on Tegra186 and later (and partially on Tegra210) > is typically static, so there is little need to reconfigure these pins. > However, there's a special case on Tegra194 where the PCIe CLKREQ and > RST pins for controller 5 may need to be reprogrammed in the kernel, > depending on whether the controller runs in endpoint mode or in root > port mode. > > This series of patches establishes the mapping of these two pins to > their GPIO equivalents and implements the code necessary to switch > between SFIO and GPIO modes when the kernel requests or releases the > GPIOs, respectively. > > Thierry > > Thierry Reding (9): > gpio: Support GPIO controllers without pin-ranges > gpio: tegra186: Add support for pin ranges > gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 > pinctrl: tegra: Fix whitespace issues for improved readability > pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo > pinctrl: tegra: Pass struct tegra_pmx for pin range check > pinctrl: tegra: Do not add default pin range on Tegra194 > pinctrl: tegra: Renumber the GG.0 and GG.1 pins > pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 > > drivers/gpio/gpio-tegra186.c | 64 ++++++++++++++++++++++++ > drivers/gpio/gpiolib.c | 5 +- > drivers/pinctrl/tegra/pinctrl-tegra.c | 52 +++++++++++++++++-- > drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +- > drivers/pinctrl/tegra/pinctrl-tegra194.c | 47 +++++++++-------- > 5 files changed, 144 insertions(+), 29 deletions(-) > > -- > 2.24.1 > Tested-by: Vidya Sagar <vidyas@nvidia.com>
On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote: > This series of patches establishes the mapping of these two pins to > their GPIO equivalents and implements the code necessary to switch > between SFIO and GPIO modes when the kernel requests or releases the > GPIOs, respectively. Is it possible to apply the gpio and pinctrl patches to each tree separately? Yours, Linus Walleij
On Fri, Mar 20, 2020 at 08:37:48PM +0100, Linus Walleij wrote: > On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote: > > > This series of patches establishes the mapping of these two pins to > > their GPIO equivalents and implements the code necessary to switch > > between SFIO and GPIO modes when the kernel requests or releases the > > GPIOs, respectively. > > Is it possible to apply the gpio and pinctrl patches to > each tree separately? Yes, that should be possible. There's a dependency from patches 2 & 3 on patch 1, but since they are all for the same tree that should be fine. The dependency also is only a runtime dependency where the GPIO driver would defer probe indefinitely because no pin range would ever be added. So as long as patches 1-3 are applied in the order given in this series, everything should be okay. Thierry
From: Thierry Reding <treding@nvidia.com> Hi, NVIDIA Tegra186 and later have a bit in the pin controller that defines whether a pin is used in special function (SFIO) mode or in general purpose (GPIO) mode. On early Tegra SoC generations, this bit was part of the GPIO controller. The pin configuration on Tegra186 and later (and partially on Tegra210) is typically static, so there is little need to reconfigure these pins. However, there's a special case on Tegra194 where the PCIe CLKREQ and RST pins for controller 5 may need to be reprogrammed in the kernel, depending on whether the controller runs in endpoint mode or in root port mode. This series of patches establishes the mapping of these two pins to their GPIO equivalents and implements the code necessary to switch between SFIO and GPIO modes when the kernel requests or releases the GPIOs, respectively. Thierry Thierry Reding (9): gpio: Support GPIO controllers without pin-ranges gpio: tegra186: Add support for pin ranges gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 pinctrl: tegra: Fix whitespace issues for improved readability pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo pinctrl: tegra: Pass struct tegra_pmx for pin range check pinctrl: tegra: Do not add default pin range on Tegra194 pinctrl: tegra: Renumber the GG.0 and GG.1 pins pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 drivers/gpio/gpio-tegra186.c | 64 ++++++++++++++++++++++++ drivers/gpio/gpiolib.c | 5 +- drivers/pinctrl/tegra/pinctrl-tegra.c | 52 +++++++++++++++++-- drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +- drivers/pinctrl/tegra/pinctrl-tegra194.c | 47 +++++++++-------- 5 files changed, 144 insertions(+), 29 deletions(-)