| Message ID | 20210804191554.1252776-1-vgupta@synopsys.com |
|---|---|
| Headers | show |
| Series | ARC atomics update | expand |
On Wed, Aug 04, 2021 at 12:15:43PM -0700, Vineet Gupta wrote: > Vineet Gupta (10): > ARC: atomics: disintegrate header > ARC: atomic: !LLSC: remove hack in atomic_set() for for UP > ARC: atomic: !LLSC: use int data type consistently > ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return > ARC: atomics: implement relaxed variants > ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines > ARC: xchg: !LLSC: remove UP micro-optimization/hack > ARC: cmpxchg/xchg: rewrite as macros to make type safe > ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) > ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants > > Will Deacon (1): > ARC: switch to generic bitops Didn't see any weird things: Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
On 8/5/21 2:02 AM, Peter Zijlstra wrote: > On Wed, Aug 04, 2021 at 12:15:43PM -0700, Vineet Gupta wrote: > >> Vineet Gupta (10): >> ARC: atomics: disintegrate header >> ARC: atomic: !LLSC: remove hack in atomic_set() for for UP >> ARC: atomic: !LLSC: use int data type consistently >> ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return >> ARC: atomics: implement relaxed variants >> ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines >> ARC: xchg: !LLSC: remove UP micro-optimization/hack >> ARC: cmpxchg/xchg: rewrite as macros to make type safe >> ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) >> ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants >> >> Will Deacon (1): >> ARC: switch to generic bitops > > Didn't see any weird things: > > Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Thx Peter. A lot of this is your code anyways ;-) Any initial thoughts/comments on patch 06/11 - is there an obvious reason that generic bitops take signed @nr or the hurdle is need to be done consistently cross-arch. -Vineet
On Thu, Aug 05, 2021 at 04:18:29PM +0000, Vineet Gupta wrote: > On 8/5/21 2:02 AM, Peter Zijlstra wrote: > > On Wed, Aug 04, 2021 at 12:15:43PM -0700, Vineet Gupta wrote: > > > >> Vineet Gupta (10): > >> ARC: atomics: disintegrate header > >> ARC: atomic: !LLSC: remove hack in atomic_set() for for UP > >> ARC: atomic: !LLSC: use int data type consistently > >> ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return > >> ARC: atomics: implement relaxed variants > >> ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines > >> ARC: xchg: !LLSC: remove UP micro-optimization/hack > >> ARC: cmpxchg/xchg: rewrite as macros to make type safe > >> ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) > >> ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants > >> > >> Will Deacon (1): > >> ARC: switch to generic bitops > > > > Didn't see any weird things: > > > > Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> > > Thx Peter. A lot of this is your code anyways ;-) > > Any initial thoughts/comments on patch 06/11 - is there an obvious > reason that generic bitops take signed @nr or the hurdle is need to be > done consistently cross-arch. That does indeed seem daft and ready for a cleanup. Will any recollection from when you touched this? AFAICT bitops/atomic.h is consistently 'unsigned int nr', but bitops/non-atomic.h is 'int nr' while bitops/instrumented-non-atomic.h is consistently 'long nr'. I'm thinking 'unsigned int nr' is the most sensible allround, but I've not gone through all the cases.
On Thu, Aug 05, 2021 at 07:04:32PM +0200, Peter Zijlstra wrote: > On Thu, Aug 05, 2021 at 04:18:29PM +0000, Vineet Gupta wrote: > > On 8/5/21 2:02 AM, Peter Zijlstra wrote: > > > On Wed, Aug 04, 2021 at 12:15:43PM -0700, Vineet Gupta wrote: > > > > > >> Vineet Gupta (10): > > >> ARC: atomics: disintegrate header > > >> ARC: atomic: !LLSC: remove hack in atomic_set() for for UP > > >> ARC: atomic: !LLSC: use int data type consistently > > >> ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return > > >> ARC: atomics: implement relaxed variants > > >> ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines > > >> ARC: xchg: !LLSC: remove UP micro-optimization/hack > > >> ARC: cmpxchg/xchg: rewrite as macros to make type safe > > >> ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) > > >> ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants > > >> > > >> Will Deacon (1): > > >> ARC: switch to generic bitops > > > > > > Didn't see any weird things: > > > > > > Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> > > > > Thx Peter. A lot of this is your code anyways ;-) > > > > Any initial thoughts/comments on patch 06/11 - is there an obvious > > reason that generic bitops take signed @nr or the hurdle is need to be > > done consistently cross-arch. > > That does indeed seem daft and ready for a cleanup. Will any > recollection from when you touched this? I had a patch to fix this but it blew up in the robot and I didn't get round to reworking it: https://lore.kernel.org/patchwork/patch/1245555/ Will
Hi, This series contains long due update to ARC atomics, discussed back in 2018 [1] and [2]. I had them for arc64 port and decided to post them here for some review and inclusion, after Mark's rework. The main changes are use of relaxed atomics and generic bitops. Latter does cause some cogen bloat on ARC due to signed args but that can be reviewd seperately consider cross-arch impact. The changes survive glibc testsuite with no regressions whatsoever. Please review and provide any feedback. Thx, -Vineet [1] https://lore.kernel.org/r/20180830144344.GW24142@hirez.programming.kicks-ass.net [2] https://lore.kernel.org/r/20180830135749.GA13005@arm.com Vineet Gupta (10): ARC: atomics: disintegrate header ARC: atomic: !LLSC: remove hack in atomic_set() for for UP ARC: atomic: !LLSC: use int data type consistently ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return ARC: atomics: implement relaxed variants ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines ARC: xchg: !LLSC: remove UP micro-optimization/hack ARC: cmpxchg/xchg: rewrite as macros to make type safe ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants Will Deacon (1): ARC: switch to generic bitops arch/arc/include/asm/atomic-llsc.h | 97 ++++++ arch/arc/include/asm/atomic-spinlock.h | 102 ++++++ arch/arc/include/asm/atomic.h | 444 ++----------------------- arch/arc/include/asm/atomic64-arcv2.h | 250 ++++++++++++++ arch/arc/include/asm/bitops.h | 188 +---------- arch/arc/include/asm/cmpxchg.h | 233 ++++++------- arch/arc/include/asm/smp.h | 14 - arch/arc/kernel/smp.c | 2 - 8 files changed, 588 insertions(+), 742 deletions(-) create mode 100644 arch/arc/include/asm/atomic-llsc.h create mode 100644 arch/arc/include/asm/atomic-spinlock.h create mode 100644 arch/arc/include/asm/atomic64-arcv2.h