diff mbox series

AArch64: correct constraint on Upl early clobber alternatives

Message ID patch-18551-tamar@arm.com
State New
Headers show
Series AArch64: correct constraint on Upl early clobber alternatives | expand

Commit Message

Tamar Christina June 6, 2024, 11:19 a.m. UTC 
Hi All,

I made an oversight in the previous patch, where I added a ?Upa
alternative to the Upl cases.  This causes it to create the tie
between the larger register file rather than the constrained one.

This fixes the affected patterns.

Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Build SPECCPU 2017 and no issues.

Ok for master?

Thanks,
Tamar

gcc/ChangeLog:

	* config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>,
	*cmp<cmp_op><mode>_cc, *cmp<cmp_op><mode>_ptest,
	@aarch64_pred_cmp<cmp_op><mode>_wide,
	*aarch64_pred_cmp<cmp_op><mode>_wide_cc,
	*aarch64_pred_cmp<cmp_op><mode>_wide_ptest): Fix Upl tie alternative.
	* config/aarch64/aarch64-sve2.md (@aarch64_pred_<sve_int_op><mode>): Fix
	Upl tie alternative.

---




--

Comments

Richard Sandiford June 6, 2024, 12:02 p.m. UTC | #1 
Tamar Christina <tamar.christina@arm.com> writes:
> Hi All,
>
> I made an oversight in the previous patch, where I added a ?Upa
> alternative to the Upl cases.  This causes it to create the tie
> between the larger register file rather than the constrained one.
>
> This fixes the affected patterns.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
> Build SPECCPU 2017 and no issues.
>
> Ok for master?
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> 	* config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>,
> 	*cmp<cmp_op><mode>_cc, *cmp<cmp_op><mode>_ptest,
> 	@aarch64_pred_cmp<cmp_op><mode>_wide,
> 	*aarch64_pred_cmp<cmp_op><mode>_wide_cc,
> 	*aarch64_pred_cmp<cmp_op><mode>_wide_ptest): Fix Upl tie alternative.
> 	* config/aarch64/aarch64-sve2.md (@aarch64_pred_<sve_int_op><mode>): Fix
> 	Upl tie alternative.

OK, thanks.  For the record...

> ---
> diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
> index d902bce62fde88b6d85f8d71f305e7fc76a4d34e..d69db34016a55b4324faa129a3ac1f47227ba776 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -8134,13 +8134,13 @@ (define_insn "@aarch64_pred_cmp<cmp_op><mode>"
>  	  UNSPEC_PRED_Z))
>     (clobber (reg:CC_NZC CC_REGNUM))]
>    "TARGET_SVE"
> -  {@ [ cons: =0 , 1   , 3 , 4            ; attrs: pred_clobber ]
> -     [ &Upa     , Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
> -     [ ?Upa     , 0Upl, w , <sve_imm_con>; yes                 ] ^
> -     [ Upa      , Upl , w , <sve_imm_con>; no                  ] ^
> -     [ &Upa     , Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
> -     [ ?Upa     , 0Upl, w , w            ; yes                 ] ^
> -     [ Upa      , Upl , w , w            ; no                  ] ^
> +  {@ [ cons: =0 , 1  , 3 , 4            ; attrs: pred_clobber ]
> +     [ &Upa     , Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
> +     [ ?Upl     , 0  , w , <sve_imm_con>; yes                 ] ^
> +     [ Upa      , Upl, w , <sve_imm_con>; no                  ] ^
> +     [ &Upa     , Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
> +     [ ?Upl     , 0  , w , w            ; yes                 ] ^
> +     [ Upa      , Upl, w , w            ; no                  ] ^
>    }
>  )
>  
> @@ -8170,13 +8170,13 @@ (define_insn_and_rewrite "*cmp<cmp_op><mode>_cc"
>  	  UNSPEC_PRED_Z))]
>    "TARGET_SVE
>     && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
> -  {@ [ cons: =0 , 1    , 2 , 3            ; attrs: pred_clobber ]
> -     [ &Upa     ,  Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
> -     [ ?Upa     ,  0Upl, w , <sve_imm_con>; yes                 ] ^
> -     [ Upa      ,  Upl , w , <sve_imm_con>; no                  ] ^
> -     [ &Upa     ,  Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
> -     [ ?Upa     ,  0Upl, w , w            ; yes                 ] ^
> -     [ Upa      ,  Upl , w , w            ; no                  ] ^
> +  {@ [ cons: =0 , 1   , 2 , 3            ; attrs: pred_clobber ]
> +     [ &Upa     ,  Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
> +     [ ?Upl     ,  0  , w , <sve_imm_con>; yes                 ] ^
> +     [ Upa      ,  Upl, w , <sve_imm_con>; no                  ] ^
> +     [ &Upa     ,  Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
> +     [ ?Upl     ,  0  , w , w            ; yes                 ] ^
> +     [ Upa      ,  Upl, w , w            ; no                  ] ^
>    }
>    "&& !rtx_equal_p (operands[4], operands[6])"
>    {
> @@ -8205,12 +8205,12 @@ (define_insn_and_rewrite "*cmp<cmp_op><mode>_ptest"
>    "TARGET_SVE
>     && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
>    {@ [ cons: =0, 1    , 2 , 3            ; attrs: pred_clobber ]
> -     [ &Upa    ,  Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
> -     [ ?Upa    ,  0Upl, w , <sve_imm_con>; yes                 ] ^
> -     [ Upa     ,  Upl , w , <sve_imm_con>; no                  ] ^
> -     [ &Upa    ,  Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
> -     [ ?Upa    ,  0Upl, w , w            ; yes                 ] ^
> -     [ Upa     ,  Upl , w , w            ; no                  ] ^
> +     [ &Upa    ,  Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
> +     [ ?Upl    ,  0  , w , <sve_imm_con>; yes                 ] ^
> +     [ Upa     ,  Upl, w , <sve_imm_con>; no                  ] ^
> +     [ &Upa    ,  Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
> +     [ ?Upl    ,  0  , w , w            ; yes                 ] ^
> +     [ Upa     ,  Upl, w , w            ; no                  ] ^
>    }
>    "&& !rtx_equal_p (operands[4], operands[6])"
>    {
> @@ -8263,10 +8263,10 @@ (define_insn "@aarch64_pred_cmp<cmp_op><mode>_wide"
>  	  UNSPEC_PRED_Z))
>     (clobber (reg:CC_NZC CC_REGNUM))]
>    "TARGET_SVE"
> -  {@ [ cons: =0, 1    , 2, 3, 4; attrs: pred_clobber ]
> -     [ &Upa    ,  Upl ,  , w, w; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
> -     [ ?Upa    ,  0Upl,  , w, w; yes                 ] ^
> -     [ Upa     ,  Upl ,  , w, w; no                  ] ^
> +  {@ [ cons: =0, 1   , 2, 3, 4; attrs: pred_clobber ]
> +     [ &Upa    ,  Upl,  , w, w; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
> +     [ ?Upl    ,  0  ,  , w, w; yes                 ] ^
> +     [ Upa     ,  Upl,  , w, w; no                  ] ^
>    }
>  )
>  
> @@ -8298,10 +8298,10 @@ (define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_cc"
>  	  UNSPEC_PRED_Z))]
>    "TARGET_SVE
>     && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
> -  {@ [ cons: =0, 1    , 2, 3, 6  ; attrs: pred_clobber ]
> -     [ &Upa    ,  Upl , w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
> -     [ ?Upa    ,  0Upl, w, w, Upl; yes                 ] ^
> -     [ Upa     ,  Upl , w, w, Upl; no                  ] ^
> +  {@ [ cons: =0, 1   , 2, 3, 6  ; attrs: pred_clobber ]
> +     [ &Upa    ,  Upl, w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
> +     [ ?Upl    ,  0  , w, w, Upl; yes                 ] ^
> +     [ Upa     ,  Upl, w, w, Upl; no                  ] ^
>    }
>  )

...these patterns are a bit of an unusual case, and were already
playing in the margins of correctness before the pred_clobber changes,
in that operand 6 is "close enough" to operand 1 that we can ignore it.
Using "Upl" for operand 6 (as in the patch) feels a bit safer than using
"0" for both operands.

Richard

>  
> @@ -8325,10 +8325,10 @@ (define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_ptest"
>     (clobber (match_scratch:<VPRED> 0))]
>    "TARGET_SVE
>     && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
> -  {@ [ cons:  =0, 1    , 2, 3, 6  ; attrs: pred_clobber ]
> -     [ &Upa     ,  Upl , w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
> -     [ ?Upa     ,  0Upl, w, w, Upl; yes                 ] ^
> -     [ Upa      ,  Upl , w, w, Upl; no                  ] ^
> +  {@ [ cons:  =0, 1   , 2, 3, 6  ; attrs: pred_clobber ]
> +     [ &Upa     ,  Upl, w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
> +     [ ?Upl     ,  0  , w, w, Upl; yes                 ] ^
> +     [ Upa      ,  Upl, w, w, Upl; no                  ] ^
>    }
>  )
>  
> diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
> index eaba9d8f25fac704c9c66e444c6249470bef3ccd..972b03a4fef0b0bd4d50edf392bcfcb9acde551e 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -3351,7 +3351,7 @@ (define_insn "@aarch64_pred_<sve_int_op><mode>"
>    "TARGET_SVE2 && TARGET_NON_STREAMING"
>    {@ [ cons: =0, 1  , 3, 4; attrs: pred_clobber ]
>       [ &Upa    , Upl, w, w; yes                 ] <sve_int_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
> -     [ ?Upa    , 0  , w, w; yes                 ] ^
> +     [ ?Upl    , 0  , w, w; yes                 ] ^
>       [ Upa     , Upl, w, w; no                  ] ^
>    }
>  )
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index d902bce62fde88b6d85f8d71f305e7fc76a4d34e..d69db34016a55b4324faa129a3ac1f47227ba776 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -8134,13 +8134,13 @@  (define_insn "@aarch64_pred_cmp<cmp_op><mode>"
 	  UNSPEC_PRED_Z))
    (clobber (reg:CC_NZC CC_REGNUM))]
   "TARGET_SVE"
-  {@ [ cons: =0 , 1   , 3 , 4            ; attrs: pred_clobber ]
-     [ &Upa     , Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
-     [ ?Upa     , 0Upl, w , <sve_imm_con>; yes                 ] ^
-     [ Upa      , Upl , w , <sve_imm_con>; no                  ] ^
-     [ &Upa     , Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
-     [ ?Upa     , 0Upl, w , w            ; yes                 ] ^
-     [ Upa      , Upl , w , w            ; no                  ] ^
+  {@ [ cons: =0 , 1  , 3 , 4            ; attrs: pred_clobber ]
+     [ &Upa     , Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
+     [ ?Upl     , 0  , w , <sve_imm_con>; yes                 ] ^
+     [ Upa      , Upl, w , <sve_imm_con>; no                  ] ^
+     [ &Upa     , Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
+     [ ?Upl     , 0  , w , w            ; yes                 ] ^
+     [ Upa      , Upl, w , w            ; no                  ] ^
   }
 )
 
@@ -8170,13 +8170,13 @@  (define_insn_and_rewrite "*cmp<cmp_op><mode>_cc"
 	  UNSPEC_PRED_Z))]
   "TARGET_SVE
    && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
-  {@ [ cons: =0 , 1    , 2 , 3            ; attrs: pred_clobber ]
-     [ &Upa     ,  Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
-     [ ?Upa     ,  0Upl, w , <sve_imm_con>; yes                 ] ^
-     [ Upa      ,  Upl , w , <sve_imm_con>; no                  ] ^
-     [ &Upa     ,  Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
-     [ ?Upa     ,  0Upl, w , w            ; yes                 ] ^
-     [ Upa      ,  Upl , w , w            ; no                  ] ^
+  {@ [ cons: =0 , 1   , 2 , 3            ; attrs: pred_clobber ]
+     [ &Upa     ,  Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
+     [ ?Upl     ,  0  , w , <sve_imm_con>; yes                 ] ^
+     [ Upa      ,  Upl, w , <sve_imm_con>; no                  ] ^
+     [ &Upa     ,  Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
+     [ ?Upl     ,  0  , w , w            ; yes                 ] ^
+     [ Upa      ,  Upl, w , w            ; no                  ] ^
   }
   "&& !rtx_equal_p (operands[4], operands[6])"
   {
@@ -8205,12 +8205,12 @@  (define_insn_and_rewrite "*cmp<cmp_op><mode>_ptest"
   "TARGET_SVE
    && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
   {@ [ cons: =0, 1    , 2 , 3            ; attrs: pred_clobber ]
-     [ &Upa    ,  Upl , w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
-     [ ?Upa    ,  0Upl, w , <sve_imm_con>; yes                 ] ^
-     [ Upa     ,  Upl , w , <sve_imm_con>; no                  ] ^
-     [ &Upa    ,  Upl , w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
-     [ ?Upa    ,  0Upl, w , w            ; yes                 ] ^
-     [ Upa     ,  Upl , w , w            ; no                  ] ^
+     [ &Upa    ,  Upl, w , <sve_imm_con>; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
+     [ ?Upl    ,  0  , w , <sve_imm_con>; yes                 ] ^
+     [ Upa     ,  Upl, w , <sve_imm_con>; no                  ] ^
+     [ &Upa    ,  Upl, w , w            ; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
+     [ ?Upl    ,  0  , w , w            ; yes                 ] ^
+     [ Upa     ,  Upl, w , w            ; no                  ] ^
   }
   "&& !rtx_equal_p (operands[4], operands[6])"
   {
@@ -8263,10 +8263,10 @@  (define_insn "@aarch64_pred_cmp<cmp_op><mode>_wide"
 	  UNSPEC_PRED_Z))
    (clobber (reg:CC_NZC CC_REGNUM))]
   "TARGET_SVE"
-  {@ [ cons: =0, 1    , 2, 3, 4; attrs: pred_clobber ]
-     [ &Upa    ,  Upl ,  , w, w; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
-     [ ?Upa    ,  0Upl,  , w, w; yes                 ] ^
-     [ Upa     ,  Upl ,  , w, w; no                  ] ^
+  {@ [ cons: =0, 1   , 2, 3, 4; attrs: pred_clobber ]
+     [ &Upa    ,  Upl,  , w, w; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
+     [ ?Upl    ,  0  ,  , w, w; yes                 ] ^
+     [ Upa     ,  Upl,  , w, w; no                  ] ^
   }
 )
 
@@ -8298,10 +8298,10 @@  (define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_cc"
 	  UNSPEC_PRED_Z))]
   "TARGET_SVE
    && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
-  {@ [ cons: =0, 1    , 2, 3, 6  ; attrs: pred_clobber ]
-     [ &Upa    ,  Upl , w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
-     [ ?Upa    ,  0Upl, w, w, Upl; yes                 ] ^
-     [ Upa     ,  Upl , w, w, Upl; no                  ] ^
+  {@ [ cons: =0, 1   , 2, 3, 6  ; attrs: pred_clobber ]
+     [ &Upa    ,  Upl, w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
+     [ ?Upl    ,  0  , w, w, Upl; yes                 ] ^
+     [ Upa     ,  Upl, w, w, Upl; no                  ] ^
   }
 )
 
@@ -8325,10 +8325,10 @@  (define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_ptest"
    (clobber (match_scratch:<VPRED> 0))]
   "TARGET_SVE
    && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
-  {@ [ cons:  =0, 1    , 2, 3, 6  ; attrs: pred_clobber ]
-     [ &Upa     ,  Upl , w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
-     [ ?Upa     ,  0Upl, w, w, Upl; yes                 ] ^
-     [ Upa      ,  Upl , w, w, Upl; no                  ] ^
+  {@ [ cons:  =0, 1   , 2, 3, 6  ; attrs: pred_clobber ]
+     [ &Upa     ,  Upl, w, w, Upl; yes                 ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
+     [ ?Upl     ,  0  , w, w, Upl; yes                 ] ^
+     [ Upa      ,  Upl, w, w, Upl; no                  ] ^
   }
 )
 
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index eaba9d8f25fac704c9c66e444c6249470bef3ccd..972b03a4fef0b0bd4d50edf392bcfcb9acde551e 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -3351,7 +3351,7 @@  (define_insn "@aarch64_pred_<sve_int_op><mode>"
   "TARGET_SVE2 && TARGET_NON_STREAMING"
   {@ [ cons: =0, 1  , 3, 4; attrs: pred_clobber ]
      [ &Upa    , Upl, w, w; yes                 ] <sve_int_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
-     [ ?Upa    , 0  , w, w; yes                 ] ^
+     [ ?Upl    , 0  , w, w; yes                 ] ^
      [ Upa     , Upl, w, w; no                  ] ^
   }
 )