Show patches with: Submitter = Tamar Christina       |    State = Action Required       |    Archived = No       |   557 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
middle-end: delay updating of dominators until later during vectorization. [PR114081] middle-end: delay updating of dominators until later during vectorization. [PR114081] - - - - --- 2024-02-25 Tamar Christina New
middle-end: update vuses out of loop which use a vdef that's moved [PR114068] middle-end: update vuses out of loop which use a vdef that's moved [PR114068] - - - - --- 2024-02-23 Tamar Christina New
AArch64: xfail modes_1.f90 [PR107071] AArch64: xfail modes_1.f90 [PR107071] - - - - --- 2024-02-15 Tamar Christina New
AArch64: remove ls64 from being mandatory on armv8.7-a.. AArch64: remove ls64 from being mandatory on armv8.7-a.. - - - - --- 2024-02-14 Tamar Christina New
middle-end: inspect all exits for additional annotations for loop. middle-end: inspect all exits for additional annotations for loop. - - - - --- 2024-02-14 Tamar Christina New
middle-end: update vector loop upper bounds when early break vect [PR113734] middle-end: update vector loop upper bounds when early break vect [PR113734] - - - - --- 2024-02-13 Tamar Christina New
middle-end: add two debug counters for early-break vectorization debugging middle-end: add two debug counters for early-break vectorization debugging - - - - --- 2024-02-08 Tamar Christina New
middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808] middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808] - - - - --- 2024-02-08 Tamar Christina New
[committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c [committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c - - - - --- 2024-02-08 Tamar Christina New
middle-end: fix ICE when destination BB for stores starts with a label [PR113750] middle-end: fix ICE when destination BB for stores starts with a label [PR113750] - - - - --- 2024-02-05 Tamar Christina New
middle-end: fix ICE when moving statements to empty BB [PR113731] middle-end: fix ICE when moving statements to empty BB [PR113731] - - - - --- 2024-02-05 Tamar Christina New
middle-end: add additional runtime test for [PR113467] middle-end: add additional runtime test for [PR113467] - - - - --- 2024-02-05 Tamar Christina New
AArch64: update vget_set_lane_1.c test output AArch64: update vget_set_lane_1.c test output - - - - --- 2024-02-01 Tamar Christina New
[2/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] [1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] - - - - --- 2024-01-31 Tamar Christina New
[1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] [1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] - - - - --- 2024-01-31 Tamar Christina New
middle-end: check memory accesses in the destination block [PR113588]. middle-end: check memory accesses in the destination block [PR113588]. - - - - --- 2024-01-29 Tamar Christina New
AArch64: relax cbranch tests to accepted inverted branches [PR113502] AArch64: relax cbranch tests to accepted inverted branches [PR113502] - - - - --- 2024-01-29 Tamar Christina New
[libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644] [libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644] - - - - --- 2024-01-29 Tamar Christina New
AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636] AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636] - - - - --- 2024-01-24 Tamar Christina New
AArch64: Do not allow SIMD clones with simdlen 1 [PR113552] AArch64: Do not allow SIMD clones with simdlen 1 [PR113552] - - - - --- 2024-01-24 Tamar Christina New
middle-end: rename main_exit_p in reduction code. middle-end: rename main_exit_p in reduction code. - - - - --- 2024-01-23 Tamar Christina New
middle-end: fix epilog reductions when vector iters peeled [PR113364] middle-end: fix epilog reductions when vector iters peeled [PR113364] - - - - --- 2024-01-23 Tamar Christina New
middle-end: remove more usages of single_exit middle-end: remove more usages of single_exit - - - - --- 2024-01-12 Tamar Christina New
middle-end testsuite: remove -save-temps from many tests [PR113319] middle-end testsuite: remove -save-temps from many tests [PR113319] - - - - --- 2024-01-11 Tamar Christina New
middle-end: make memory analysis for early break more deterministic [PR113135] middle-end: make memory analysis for early break more deterministic [PR113135] - - - - --- 2024-01-11 Tamar Christina New
middle-end: fill in reduction PHI for all alt exits [PR113144] middle-end: fill in reduction PHI for all alt exits [PR113144] - - - - --- 2024-01-11 Tamar Christina New
[testsuite] : Make bitint early vect test more accurate [testsuite] : Make bitint early vect test more accurate - - - - --- 2024-01-10 Tamar Christina New
middle-end: correctly identify the edge taken when condition is true. [PR113287] middle-end: correctly identify the edge taken when condition is true. [PR113287] - - - - --- 2024-01-10 Tamar Christina New
[committed,c++,frontend] : initialize ivdep value [committed,c++,frontend] : initialize ivdep value - - - - --- 2024-01-10 Tamar Christina New
[committed] middle-end: removed unused variable in vectorizable_live_operation_1 [committed] middle-end: removed unused variable in vectorizable_live_operation_1 - - - - --- 2024-01-09 Tamar Christina New
Arm: Update early-break tests to accept thumb output too. Arm: Update early-break tests to accept thumb output too. - - - - --- 2024-01-09 Tamar Christina New
[frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267] [frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267] - - - - --- 2024-01-08 Tamar Christina New
middle-end: thread through existing LCSSA variable for alternative exits too [PR113237] middle-end: thread through existing LCSSA variable for alternative exits too [PR113237] - - - - --- 2024-01-07 Tamar Christina New
middle-end: Don't apply copysign optimization if target does not implement optab [PR112468] middle-end: Don't apply copysign optimization if target does not implement optab [PR112468] - - - - --- 2024-01-04 Tamar Christina New
middle-end: check if target can do extract first for early breaks [PR113199] middle-end: check if target can do extract first for early breaks [PR113199] - - - - --- 2024-01-02 Tamar Christina New
middle-end: maintain LCSSA form when peeled vector iterations have virtual operands middle-end: maintain LCSSA form when peeled vector iterations have virtual operands - - - - --- 2023-12-29 Tamar Christina New
middle-end: Fix dominators updates when peeling with multiple exits [PR113144] middle-end: Fix dominators updates when peeling with multiple exits [PR113144] - - - - --- 2023-12-29 Tamar Christina New
middle-end: rejects loops with nonlinear inductions and early breaks [PR113163] middle-end: rejects loops with nonlinear inductions and early breaks [PR113163] - - - - --- 2023-12-29 Tamar Christina New
[20/21] Arm: Add Advanced SIMD cbranch implementation Untitled series #388362 - - - - --- 2023-12-29 Tamar Christina New
AArch64 Update costing for vector conversions [PR110625] AArch64 Update costing for vector conversions [PR110625] - - - - --- 2023-12-29 Tamar Christina New
[committed] middle-end: explicitly initialize vec_stmts [PR113132] [committed] middle-end: explicitly initialize vec_stmts [PR113132] - - - - --- 2023-12-25 Tamar Christina New
[testsuite] : Add more pragma novector to new tests [testsuite] : Add more pragma novector to new tests - - - - --- 2023-12-24 Tamar Christina New
[2/21] middle-end testsuite: Add tests for early break vectorization Untitled series #387734 - - - - --- 2023-12-21 Tamar Christina New
middle-end: Handle hybrid SLP induction vectorization with early breaks. middle-end: Handle hybrid SLP induction vectorization with early breaks. - - - - --- 2023-12-19 Tamar Christina New
middle-end: Mark all control flow as used_in_scope. middle-end: Mark all control flow as used_in_scope. - - - - --- 2023-12-11 Tamar Christina New
middle-end: Fix peeled vect loop IV values. middle-end: Fix peeled vect loop IV values. - - - - --- 2023-12-06 Tamar Christina New
middle-end: correct loop bounds for early breaks and peeled vector loops middle-end: correct loop bounds for early breaks and peeled vector loops - - - - --- 2023-12-06 Tamar Christina New
middle-end: refactor vectorizable_live_operation into helper method for codegen middle-end: refactor vectorizable_live_operation into helper method for codegen - - - - --- 2023-11-27 Tamar Christina New
middle-end: prevent LIM from hoising vector compares from gconds if target does not support it. middle-end: prevent LIM from hoising vector compares from gconds if target does not support it. - - - - --- 2023-11-27 Tamar Christina New
AArch64: fix aarch64_usubw pattern AArch64: fix aarch64_usubw pattern - - - - --- 2023-11-22 Tamar Christina New
AArch64 docs: update -mcpu=generic definition on aarch64 AArch64 docs: update -mcpu=generic definition on aarch64 - - - - --- 2023-11-16 Tamar Christina New
[6/6] AArch64: only emit mismatch error when features would be disabled. [1/6] AArch64: Refactor costs models to different files. - - - - --- 2023-11-15 Tamar Christina New
[4/6] AArch64: Add new generic-armv9-a CPU and make it the default for Armv9 [1/6] AArch64: Refactor costs models to different files. - - - - --- 2023-11-15 Tamar Christina New
[3/6] AArch64: Add new generic-armv8-a CPU and make it the default. [1/6] AArch64: Refactor costs models to different files. - - - - --- 2023-11-15 Tamar Christina New
[2/6] AArch64: Remove special handling of generic cpu. [1/6] AArch64: Refactor costs models to different files. - - - - --- 2023-11-15 Tamar Christina New
[1/6] AArch64: Refactor costs models to different files. [1/6] AArch64: Refactor costs models to different files. - - - - --- 2023-11-15 Tamar Christina New
AArch64: only discount MLA for vector and scalar statements AArch64: only discount MLA for vector and scalar statements - - - - --- 2023-11-15 Tamar Christina New
AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2} AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2} - - - - --- 2023-11-15 Tamar Christina New
middle-end: skip checking loop exits if loop malformed [PR111878] middle-end: skip checking loop exits if loop malformed [PR111878] - - - - --- 2023-11-15 Tamar Christina New
[v3,2/2] middle-end match.pd: optimize fneg (fabs (x)) to copysign (x, -1) [PR109154] [v3,1/2] middle-end: expand copysign handling from lockstep to nested iters - - - - --- 2023-11-06 Tamar Christina New
[v3,1/2] middle-end: expand copysign handling from lockstep to nested iters [v3,1/2] middle-end: expand copysign handling from lockstep to nested iters - - - - --- 2023-11-06 Tamar Christina New
[21/21] Arm: Add MVE cbranch implementation Support early break/return auto-vectorization - - - - --- 2023-11-06 Tamar Christina New
[20/21] Arm: Add Advanced SIMD cbranch implementation Support early break/return auto-vectorization - - - - --- 2023-11-06 Tamar Christina New
[19/21] AArch64: Add optimization for vector cbranch combining SVE and Advanced SIMD Untitled series #380863 - - - - --- 2023-11-06 Tamar Christina New
[18/21] AArch64: Add optimization for vector != cbranch fed into compare with 0 for Advanced SIMD Untitled series #380862 - - - - --- 2023-11-06 Tamar Christina New
[17/21] AArch64: Add implementation for vector cbranch for Advanced SIMD Untitled series #380861 - - - - --- 2023-11-06 Tamar Christina New
[16/21] middle-end testsuite: un-xfail TSVC loops that check for exit control flow vectorization Untitled series #380860 - - - - --- 2023-11-06 Tamar Christina New
[15/21] middle-end: [RFC] conditionally support forcing final edge for debugging Untitled series #380859 - - - - --- 2023-11-06 Tamar Christina New
[14/21] middle-end: Change loop analysis from looking at at number of BB to actual cfg Untitled series #380858 - - - - --- 2023-11-06 Tamar Christina New
[13/21] middle-end: Update loop form analysis to support early break Untitled series #380857 - - - - --- 2023-11-06 Tamar Christina New
[12/21] middle-end: Add remaining changes to peeling and vectorizer to support early breaks Untitled series #380856 - - - - --- 2023-11-06 Tamar Christina New
[11/21] middle-end: wire through peeling changes and dominator updates after guard edge split Untitled series #380855 - - - - --- 2023-11-06 Tamar Christina New
[10/21] middle-end: implement relevancy analysis support for control flow Untitled series #380853 - - - - --- 2023-11-06 Tamar Christina New
[9/21] middle-end: implement vectorizable_early_exit for codegen of exit code Untitled series #380854 - - - - --- 2023-11-06 Tamar Christina New
[8/21] middle-end: update vectorizable_live_reduction with support for multiple exits and different… Untitled series #380852 - - - - --- 2023-11-06 Tamar Christina New
[7/21] middle-end: update IV update code to support early breaks and arbitrary exits Untitled series #380851 - - - - --- 2023-11-06 Tamar Christina New
[6/21] middle-end: support multiple exits in loop versioning Untitled series #380849 - - - - --- 2023-11-06 Tamar Christina New
[5/21] middle-end: update vectorizer's control update to support picking an exit other than loop la… Untitled series #380850 - - - - --- 2023-11-06 Tamar Christina New
[4/21] middle-end: update loop peeling code to maintain LCSSA form for early breaks Untitled series #380848 - - - - --- 2023-11-06 Tamar Christina New
[3/21] middle-end: Implement code motion and dependency analysis for early breaks Support early break/return auto-vectorization - - - - --- 2023-11-06 Tamar Christina New
[2/21] middle-end testsuite: Add tests for early break vectorization Untitled series #380847 - - - - --- 2023-11-06 Tamar Christina New
[1/21] middle-end testsuite: Add more pragma novector to new tests [1/21] middle-end testsuite: Add more pragma novector to new tests - - - - --- 2023-11-06 Tamar Christina New
middle-end: don't keep .MEM guard nodes for PHI nodes who dominate loop [PR111860] middle-end: don't keep .MEM guard nodes for PHI nodes who dominate loop [PR111860] - - - - --- 2023-10-20 Tamar Christina New
middle-end: don't pass loop_vinfo to vect_set_loop_condition during prolog peeling [PR111866] middle-end: don't pass loop_vinfo to vect_set_loop_condition during prolog peeling [PR111866] - - - - --- 2023-10-20 Tamar Christina New
middle-end: don't create LC-SSA PHI variables for PHI nodes who dominate loop middle-end: don't create LC-SSA PHI variables for PHI nodes who dominate loop - - - - --- 2023-10-19 Tamar Christina New
[5/6] AArch64: Fix Armv9-a warnings that get emitted whenever a ACLE header is used. Untitled series #377342 - - - - --- 2023-10-12 Tamar Christina New
AArch64 Add SVE implementation for cond_copysign. AArch64 Add SVE implementation for cond_copysign. - - - - --- 2023-10-05 Tamar Christina New
middle-end ifcvt: Add support for conditional copysign middle-end ifcvt: Add support for conditional copysign - - - - --- 2023-10-05 Tamar Christina New
AArch64 Handle copysign (x, -1) expansion efficiently AArch64 Handle copysign (x, -1) expansion efficiently - - - - --- 2023-10-05 Tamar Christina New
middle-end ifcvt: Allow any const IFN in conditional blocks middle-end ifcvt: Allow any const IFN in conditional blocks - - - - --- 2023-10-05 Tamar Christina New
middle-end: Recursively check is_trivially_copyable_or_pair in vec.h middle-end: Recursively check is_trivially_copyable_or_pair in vec.h - - - - --- 2023-10-02 Tamar Christina New
[3/3] middle-end: maintain LCSSA throughout loop peeling [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - - --- 2023-10-02 Tamar Christina New
[2/3] middle-end: updated niters analysis to handle multiple exits. [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - - --- 2023-10-02 Tamar Christina New
[1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - - --- 2023-10-02 Tamar Christina New
AArch64 Rewrite simd move immediate patterns to new syntax AArch64 Rewrite simd move immediate patterns to new syntax - - 1 - --- 2023-09-27 Tamar Christina New
AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] - - - - --- 2023-09-27 Tamar Christina New
AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] - - - - --- 2023-09-27 Tamar Christina New
AArch64 Add movi for 0 moves for scalar types [PR109154] AArch64 Add movi for 0 moves for scalar types [PR109154] - - - - --- 2023-09-27 Tamar Christina New
middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154] middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154] - - - - --- 2023-09-27 Tamar Christina New
middle-end Fold vec_cond into conditional ternary or binary operation when sharing operand [PR10915… middle-end Fold vec_cond into conditional ternary or binary operation when sharing operand [PR10915… - - - - --- 2023-09-27 Tamar Christina New
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