Show patches with: Submitter = Tamar Christina       |    State = Action Required       |    Archived = No       |   646 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
AArch64: don't override march to assembler with mcpu if march is specified [PR110901] AArch64: don't override march to assembler with mcpu if march is specified [PR110901] - - - - --- 2025-01-11 Tamar Christina New
AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR113… AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR113… - - - - --- 2025-01-11 Tamar Christina New
[libstdc++] : backport inline keyword on std::find [libstdc++] : backport inline keyword on std::find - - - - --- 2025-01-10 Tamar Christina New
AArch64: correct Cortex-X4 MIDR AArch64: correct Cortex-X4 MIDR - - - - --- 2025-01-09 Tamar Christina New
AArch64: Implement four and eight chunk VLA concats [PR118272] AArch64: Implement four and eight chunk VLA concats [PR118272] - - - - --- 2025-01-02 Tamar Christina New
AArch64: Fix costing of emulated gathers/scatters [PR118188] AArch64: Fix costing of emulated gathers/scatters [PR118188] - - - - --- 2025-01-02 Tamar Christina New
Arm: [committed] fix bootstrap after MVE changes Arm: [committed] fix bootstrap after MVE changes - - - - --- 2024-12-15 Tamar Christina New
[2/2,libstdc++] : Adjust probabilities of hashmap loop conditions [1/2,libstdc++] : Add inline keyword to _M_locate - - - - --- 2024-12-13 Tamar Christina New
[1/2,libstdc++] : Add inline keyword to _M_locate [1/2,libstdc++] : Add inline keyword to _M_locate - - - - --- 2024-12-13 Tamar Christina New
[2/2] AArch64: Set L1 data cache size according to size on CPUs [1/2] AArch64: Add CMP+CSEL and CMP+CSET for cores that support it - - - - --- 2024-12-11 Tamar Christina New
[1/2] AArch64: Add CMP+CSEL and CMP+CSET for cores that support it [1/2] AArch64: Add CMP+CSEL and CMP+CSET for cores that support it - - - - --- 2024-12-11 Tamar Christina New
[7/7] AArch64: Implement vector concat of partial SVE vectors Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
[6/7] middle-end: add vec_init support for variable length subvector concatenation. Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
[5/7] middle-end: Add initial support for poly_int64 BIT_FIELD_REF in expand pass [PR96342] Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
[4/7] middle-end: Fix mask length arg in call to vect_get_loop_mask [PR96342] Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
[3/7] AArch64: Disable `omp declare variant' tests for aarch64 [PR96342] Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
[2/7] AArch64: Add SVE support for simd clones [PR96342] Untitled series #435243 - - - - --- 2024-12-04 Tamar Christina New
middle-end: rework vectorizable_store to iterate over single index [PR117557] middle-end: rework vectorizable_store to iterate over single index [PR117557] - - - - --- 2024-11-27 Tamar Christina New
[middle-end] For multiplication try swapping operands when matching complex multiply [PR116463] [middle-end] For multiplication try swapping operands when matching complex multiply [PR116463] - - - - --- 2024-11-21 Tamar Christina New
middle-end: Pass along SLP node when costing vector loads/stores middle-end: Pass along SLP node when costing vector loads/stores - - - - --- 2024-11-20 Tamar Christina New
AArch64 Suppress default options when march or mcpu used is not affected by it. AArch64 Suppress default options when march or mcpu used is not affected by it. - - - - --- 2024-11-15 Tamar Christina New
AArch64 backport Neoverse and Cortex CPU definitions AArch64 backport Neoverse and Cortex CPU definitions - - - - --- 2024-11-08 Tamar Christina New
middle-end: Handle more gcond lowering [PR117176] middle-end: Handle more gcond lowering [PR117176] - - - - --- 2024-10-21 Tamar Christina New
middle-end: Fix GSI for gcond root [PR117140] middle-end: Fix GSI for gcond root [PR117140] - - - - --- 2024-10-18 Tamar Christina New
AArch64 re-enable memory access costing after SLP change. AArch64 re-enable memory access costing after SLP change. - - - - --- 2024-10-15 Tamar Christina New
[4/4] middle-end: create the longest possible zero extend chain after overwidening [1/4] middle-end: support multi-step zero-extends using VEC_PERM_EXPR - - - - --- 2024-10-14 Tamar Christina New
[3/4] AArch64: enable zero-extends using TBLs for Adv. SIMD [1/4] middle-end: support multi-step zero-extends using VEC_PERM_EXPR - - - - --- 2024-10-14 Tamar Christina New
[2/4] middle-end: Fix VEC_PERM_EXPR lowering since relaxation of vector sizes [1/4] middle-end: support multi-step zero-extends using VEC_PERM_EXPR - - - - --- 2024-10-14 Tamar Christina New
[1/4] middle-end: support multi-step zero-extends using VEC_PERM_EXPR [1/4] middle-end: support multi-step zero-extends using VEC_PERM_EXPR - - - - --- 2024-10-14 Tamar Christina New
[3/3] AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0 [1/3] AArch64: update testsuite to account for new zero moves - - - - --- 2024-10-14 Tamar Christina New
[2/3] AArch64: support encoding integer immediates using floating point moves [1/3] AArch64: update testsuite to account for new zero moves - - - - --- 2024-10-14 Tamar Christina New
[1/3] AArch64: update testsuite to account for new zero moves [1/3] AArch64: update testsuite to account for new zero moves - - - - --- 2024-10-14 Tamar Christina New
middle-end: Save VMAT info in stmt_vec_info as well for SLP for costing. middle-end: Save VMAT info in stmt_vec_info as well for SLP for costing. - - - - --- 2024-10-14 Tamar Christina New
AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371] AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371] - - - - --- 2024-10-14 Tamar Christina New
[simplify-rtx] : Fix incorrect folding of shift and AND [PR117012] [simplify-rtx] : Fix incorrect folding of shift and AND [PR117012] - - - - --- 2024-10-14 Tamar Christina New
middle-end: copy STMT_VINFO_STRIDED_P when DR is replaced [PR116956] middle-end: copy STMT_VINFO_STRIDED_P when DR is replaced [PR116956] - - - - --- 2024-10-14 Tamar Christina New
middle-end: support SLP early break middle-end: support SLP early break - - - - --- 2024-10-01 Tamar Christina New
[2/2] AArch64: support encoding integer immediates using floating point moves [1/2] AArch64: refactor aarch64_float_const_representable_p to take additional mode param - - - - --- 2024-09-30 Tamar Christina New
[1/2] AArch64: refactor aarch64_float_const_representable_p to take additional mode param [1/2] AArch64: refactor aarch64_float_const_representable_p to take additional mode param - - - - --- 2024-09-30 Tamar Christina New
middle-end: check explicitly for external or constants when checking for loop invariant [PR116817] middle-end: check explicitly for external or constants when checking for loop invariant [PR116817] - - - - --- 2024-09-23 Tamar Christina New
middle-end: Insert invariant instructions before the gsi [PR116812[ middle-end: Insert invariant instructions before the gsi [PR116812[ - - - - --- 2024-09-23 Tamar Christina New
[testsuite] : Update commandline for PR116628.c to use neoverse-v2 [PR116628] [testsuite] : Update commandline for PR116628.c to use neoverse-v2 [PR116628] - - - - --- 2024-09-20 Tamar Christina New
AArch64: Take into account when VF is higher than known scalar iters AArch64: Take into account when VF is higher than known scalar iters - - - - --- 2024-09-20 Tamar Christina New
middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628] middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628] - - - - --- 2024-09-06 Tamar Christina New
[4/4] AArch64: Define VECTOR_STORE_FLAG_VALUE. [1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available - - - - --- 2024-09-03 Tamar Christina New
[3/4,rtl] : simplify boolean vector EQ and NE comparisons [1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available - - - - --- 2024-09-03 Tamar Christina New
[2/4] middle-end: lower COND_EXPR into gimple form in vect_recog_bool_pattern [1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available - - - - --- 2024-09-03 Tamar Christina New
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available [1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available - - - - --- 2024-09-03 Tamar Christina New
[docs] : [committed] remove double mention of armv9-a. [docs] : [committed] remove double mention of armv9-a. - - - - --- 2024-09-03 Tamar Christina New
[testsuite] : remove -fwrapv from signbit-5.c [testsuite] : remove -fwrapv from signbit-5.c - - - - --- 2024-09-03 Tamar Christina New
[2/2] middle-end: use two's complement equality when comparing IVs during candidate selection [PR11… [1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932] - - - - --- 2024-08-20 Tamar Christina New
[1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932] [1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932] - - - - --- 2024-08-20 Tamar Christina New
AArch64: Fix signbit mask creation after late combine [PR116229] AArch64: Fix signbit mask creation after late combine [PR116229] - - - - --- 2024-08-07 Tamar Christina New
middle-end: check for vector mode before in get_mask_mode [PR116074] middle-end: check for vector mode before in get_mask_mode [PR116074] - - - - --- 2024-07-26 Tamar Christina New
[8/8] AArch64: take gather/scatter decode overhead into account [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[7/8] AArch64: Add Cortex-X925 core definition and cost model [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[6/8] AArch64: Update Neoverse N2 cost model to release costs [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[5/8] AArch64: Update Generic Armv9-a cost model to release costs [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[4/8] AArch64: Add Neoverse N3 and Cortex-A725 core definition and cost model [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[3/8] AArch64: Add Neoverse V3AE core definition and cost model [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[2/8] AArch64: Add Neoverse V3 core definition and cost model [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
[1/8] AArch64: Update Neoverse V2 cost model to release costs [1/8] AArch64: Update Neoverse V2 cost model to release costs - - - - --- 2024-07-26 Tamar Christina New
AArch64: check for vector mode in get_mask_mode [PR116074] AArch64: check for vector mode in get_mask_mode [PR116074] - - - - --- 2024-07-26 Tamar Christina New
[contrib] : support json output from check_GNU_style_lib.py [contrib] : support json output from check_GNU_style_lib.py - - - - --- 2024-07-18 Tamar Christina New
middle-end: fix 0 offset creation and folding [PR115936] middle-end: fix 0 offset creation and folding [PR115936] - - - - --- 2024-07-16 Tamar Christina New
[2/2] AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531]. Untitled series #414603 - - - - --- 2024-07-10 Tamar Christina New
[2/2] AArch64: lower 2 reg TBL permutes with one zero register to 1 reg TBL. [1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent. - - - - --- 2024-07-04 Tamar Christina New
[1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent. [1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent. - - - - --- 2024-07-04 Tamar Christina New
[committed,testsuite] : Update test for PR115537 to use SVE . [committed,testsuite] : Update test for PR115537 to use SVE . - - - - --- 2024-07-04 Tamar Christina New
[2/2] middle-end: replace constant_multiple_of with aff_combination_constant_multiple_p [PR114932] [1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932] - - - - --- 2024-07-01 Tamar Christina New
[1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932] [1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932] - - - - --- 2024-07-01 Tamar Christina New
middle-end: Implement conditonal store vectorizer pattern [PR115531] middle-end: Implement conditonal store vectorizer pattern [PR115531] - - - - --- 2024-06-25 Tamar Christina New
[c++,frontend] : check for missing condition for novector [PR115623] [c++,frontend] : check for missing condition for novector [PR115623] - - - - --- 2024-06-25 Tamar Christina New
[ivopts] : use affine_tree when comparing IVs during candidate selection [PR114932] [ivopts] : use affine_tree when comparing IVs during candidate selection [PR114932] - - - - --- 2024-06-14 Tamar Christina New
[ivopts] : perform affine fold on unsigned addressing modes known not to overflow. [PR114932] [ivopts] : perform affine fold on unsigned addressing modes known not to overflow. [PR114932] - - - - --- 2024-06-14 Tamar Christina New
AArch64: correct constraint on Upl early clobber alternatives AArch64: correct constraint on Upl early clobber alternatives - - - - --- 2024-06-06 Tamar Christina New
[4/4] AArch64: enable new predicate tuning for Neoverse cores. Untitled series #407712 - - - - --- 2024-05-22 Tamar Christina New
[3/4] AArch64: add new alternative with early clobber to patterns Untitled series #407712 - - - - --- 2024-05-22 Tamar Christina New
[4/4] AArch64: enable new predicate tuning for Neoverse cores. AArch64: support conditional early clobbers on certain operations. - - - - --- 2024-05-15 Tamar Christina New
[3/4] AArch64: add new alternative with early clobber to patterns AArch64: support conditional early clobbers on certain operations. - - - - --- 2024-05-15 Tamar Christina New
[2/4] AArch64: add new tuning param and attribute for enabling conditional early clobber AArch64: support conditional early clobbers on certain operations. - - - - --- 2024-05-15 Tamar Christina New
[1/4] AArch64: convert several predicate patterns to new compact syntax AArch64: support conditional early clobbers on certain operations. - - - - --- 2024-05-15 Tamar Christina New
middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769] middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769] - - - - --- 2024-04-19 Tamar Christina New
AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741] AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741] - - - - --- 2024-04-18 Tamar Christina New
middle-end: skip vectorization check on ilp32 on vect-early-break_124-pr114403.c middle-end: skip vectorization check on ilp32 on vect-early-break_124-pr114403.c - - - - --- 2024-04-16 Tamar Christina New
docs: document early break support and pragma novector docs: document early break support and pragma novector - - - - --- 2024-04-16 Tamar Christina New
middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403]. middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403]. - - - - --- 2024-04-12 Tamar Christina New
middle-end vect: adjust loop upper bounds when peeling for gaps and early break [PR114403] middle-end vect: adjust loop upper bounds when peeling for gaps and early break [PR114403] - - - - --- 2024-04-04 Tamar Christina New
Summary: [PATCH][committed]AArch64: Do not allow SIMD clones with simdlen 1 [PR113552][GCC 13/12/11… Summary: [PATCH][committed]AArch64: Do not allow SIMD clones with simdlen 1 [PR113552][GCC 13/12/11… - - - - --- 2024-03-12 Tamar Christina New
middle-end: delay updating of dominators until later during vectorization. [PR114081] middle-end: delay updating of dominators until later during vectorization. [PR114081] - - - - --- 2024-02-25 Tamar Christina New
middle-end: update vuses out of loop which use a vdef that's moved [PR114068] middle-end: update vuses out of loop which use a vdef that's moved [PR114068] - - - - --- 2024-02-23 Tamar Christina New
AArch64: xfail modes_1.f90 [PR107071] AArch64: xfail modes_1.f90 [PR107071] - - - - --- 2024-02-15 Tamar Christina New
AArch64: remove ls64 from being mandatory on armv8.7-a.. AArch64: remove ls64 from being mandatory on armv8.7-a.. - - - - --- 2024-02-14 Tamar Christina New
middle-end: inspect all exits for additional annotations for loop. middle-end: inspect all exits for additional annotations for loop. - - - - --- 2024-02-14 Tamar Christina New
middle-end: update vector loop upper bounds when early break vect [PR113734] middle-end: update vector loop upper bounds when early break vect [PR113734] - - - - --- 2024-02-13 Tamar Christina New
middle-end: add two debug counters for early-break vectorization debugging middle-end: add two debug counters for early-break vectorization debugging - - - - --- 2024-02-08 Tamar Christina New
middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808] middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808] - - - - --- 2024-02-08 Tamar Christina New
[committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c [committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c - - - - --- 2024-02-08 Tamar Christina New
middle-end: fix ICE when destination BB for stores starts with a label [PR113750] middle-end: fix ICE when destination BB for stores starts with a label [PR113750] - - - - --- 2024-02-05 Tamar Christina New
middle-end: fix ICE when moving statements to empty BB [PR113731] middle-end: fix ICE when moving statements to empty BB [PR113731] - - - - --- 2024-02-05 Tamar Christina New
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