Message ID | patch-16700-tamar@arm.com |
---|---|
State | New |
Headers | show |
Series | AArch64 Fix ILP32 tbranch | expand |
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: Tuesday, December 13, 2022 5:14 PM > To: gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Kyrylo Tkachov > <Kyrylo.Tkachov@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: [PATCH]AArch64 Fix ILP32 tbranch > > Hi All, > > the baremetal builds are currently broken because the shift ends up in the > wrong > representation if the mode is SImode and the shift amount if 31. To fix this > create the rtx constant with an explicit mode so the backend passes know > which > representation it needs to take. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > Build aarch64-none-elf with ILP32 multilib and no issues > > Ok for master? Ok. Thanks, Kyrill > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (tbranch_<code><mode>3): Use > gen_int_mode. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64.md > b/gcc/config/aarch64/aarch64.md > index > d749c98eef63de4b92e589a167af823416f6a71d..6c27fb89e663d6ed845b41da > f32476c2a58a169c 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -957,7 +957,7 @@ (define_expand "tbranch_<code><mode>3" > { > rtx bitvalue = gen_reg_rtx (<ZEROM>mode); > rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); > - rtx val = GEN_INT (1UL << UINTVAL (operands[1])); > + rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), > <MODE>mode); > emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); > operands[1] = const0_rtx; > operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue, > > > > > --
--- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -957,7 +957,7 @@ (define_expand "tbranch_<code><mode>3" { rtx bitvalue = gen_reg_rtx (<ZEROM>mode); rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); - rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode); emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); operands[1] = const0_rtx; operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue,