diff mbox

[rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

Message ID d94533d9-e003-bb5f-9f68-bca98a7ecbde@vnet.ibm.com
State New
Headers show

Commit Message

Peter Bergner Jan. 18, 2017, 8:38 p.m. UTC 
This is a partial patch for PR78516.  This patch fixes some broken constraints
in spe.md that were exposed by the rs6000 port's switch to using LRA.
In order to change some of the constraints to outputs from inout, I had
to change some of the instructions we emit to equivalent forms.

Joseph has said this patch is enough to allow the SPE build to finish.
We still have an outstanding ICE while building glibc.  That looks like a
latent LRA bug.  We have a "fix" that allows SPE to build glibc, but
unfortunately, it causes an ICE while bootstrapping a powerpc64le-linux gcc.
I'm am tracking that down, but that will not make GCC 7.

Is this ok for trunk?

Peter

	PR target/78516
	* config/rs6000/spe.md (mov_si<mode>_e500_subreg0): Fix constraints.
	Use the evmergelohi instruction.
	(mov_si<mode>_e500_subreg4_2_le): Likewise.
	(mov_sitf_e500_subreg8_2_be): Likewise.
	(mov_sitf_e500_subreg12_2_le): Likewise.
	(mov_si<mode>_e500_subreg0_2_le): Fix constraints.
	(mov_si<mode>_e500_subreg4_2_be): Likewise.
	(mov_sitf_e500_subreg8_2_le): Likewise.
	(mov_sitf_e500_subreg12_2_be): Likewise.

Comments

Segher Boessenkool Jan. 19, 2017, 2:04 a.m. UTC | #1 
On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote:
> This is a partial patch for PR78516.  This patch fixes some broken constraints
> in spe.md that were exposed by the rs6000 port's switch to using LRA.
> In order to change some of the constraints to outputs from inout, I had
> to change some of the instructions we emit to equivalent forms.
> 
> Joseph has said this patch is enough to allow the SPE build to finish.
> We still have an outstanding ICE while building glibc.  That looks like a
> latent LRA bug.  We have a "fix" that allows SPE to build glibc, but
> unfortunately, it causes an ICE while bootstrapping a powerpc64le-linux gcc.
> I'm am tracking that down, but that will not make GCC 7.
> 
> Is this ok for trunk?

This looks good, please apply.  Thanks,


Segher


> 	PR target/78516
> 	* config/rs6000/spe.md (mov_si<mode>_e500_subreg0): Fix constraints.
> 	Use the evmergelohi instruction.
> 	(mov_si<mode>_e500_subreg4_2_le): Likewise.
> 	(mov_sitf_e500_subreg8_2_be): Likewise.
> 	(mov_sitf_e500_subreg12_2_le): Likewise.
> 	(mov_si<mode>_e500_subreg0_2_le): Fix constraints.
> 	(mov_si<mode>_e500_subreg4_2_be): Likewise.
> 	(mov_sitf_e500_subreg8_2_le): Likewise.
> 	(mov_sitf_e500_subreg12_2_be): Likewise.
Peter Bergner Jan. 19, 2017, 2:24 a.m. UTC | #2 
On 1/18/17 8:04 PM, Segher Boessenkool wrote:
> On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote:
>>
>> Is this ok for trunk?
>
> This looks good, please apply.  Thanks,

Thanks, committed as revision 244609.

Peter
diff mbox

Patch

Index: gcc/config/rs6000/spe.md
===================================================================
--- gcc/config/rs6000/spe.md	(revision 243444)
+++ gcc/config/rs6000/spe.md	(working copy)
@@ -2559,19 +2559,19 @@  (define_insn "*mov_si<mode>_e500_subreg0
 ;; ??? Could use evstwwe for memory stores in some cases, depending on
 ;; the offset.
 (define_insn "*mov_si<mode>_e500_subreg0_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
   "WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
   "@
-   evmergehi %0,%0,%1
+   evmergelohi %0,%1,%1
    evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
   [(set_attr "length" "4,8")])
 
 (define_insn "*mov_si<mode>_e500_subreg0_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
-	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,r") 0))]
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
+	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))]
   "!WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
@@ -2630,7 +2630,7 @@  (define_insn_and_split "*mov_si<mode>_e5
   [(set_attr "length" "8")])
 
 (define_insn "*mov_si<mode>_e500_subreg4_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
   "WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
@@ -2640,13 +2640,13 @@  (define_insn "*mov_si<mode>_e500_subreg4
    stw%U0%X0 %1,%0")
 
 (define_insn "*mov_si<mode>_e500_subreg4_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))]
   "!WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
   "@
-   evmergehi %0,%0,%1
+   evmergelohi %0,%1,%1
    evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
   [(set_attr "length" "4,8")])
 
@@ -2668,16 +2668,16 @@  (define_insn "*mov_sitf_e500_subreg8_le"
    lwz%U1%X1 %L0,%1")
 
 (define_insn "*mov_sitf_e500_subreg8_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
   "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
-   evmergehi %0,%0,%L1
+   evmergelohi %0,%L1,%L1
    evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
   [(set_attr "length" "4,8")])
 
 (define_insn "*mov_sitf_e500_subreg8_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))]
   "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
@@ -2702,7 +2702,7 @@  (define_insn "*mov_sitf_e500_subreg12_le
   [(set_attr "length" "4,12")])
 
 (define_insn "*mov_sitf_e500_subreg12_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
   "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
@@ -2710,11 +2710,11 @@  (define_insn "*mov_sitf_e500_subreg12_2_
    stw%U0%X0 %L1,%0")
 
 (define_insn "*mov_sitf_e500_subreg12_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))]
   "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
-   evmergehi %0,%0,%L1
+   evmergelohi %0,%L1,%L1
    evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
   [(set_attr "length" "4,8")])