Index: gcc/config/rs6000/spe.md
===================================================================
--- gcc/config/rs6000/spe.md	(revision 243444)
+++ gcc/config/rs6000/spe.md	(working copy)
@@ -2559,19 +2559,19 @@ (define_insn "*mov_si<mode>_e500_subreg0
 ;; ??? Could use evstwwe for memory stores in some cases, depending on
 ;; the offset.
 (define_insn "*mov_si<mode>_e500_subreg0_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
   "WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
   "@
-   evmergehi %0,%0,%1
+   evmergelohi %0,%1,%1
    evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
   [(set_attr "length" "4,8")])
 
 (define_insn "*mov_si<mode>_e500_subreg0_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
-	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,r") 0))]
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
+	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))]
   "!WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
@@ -2630,7 +2630,7 @@ (define_insn_and_split "*mov_si<mode>_e5
   [(set_attr "length" "8")])
 
 (define_insn "*mov_si<mode>_e500_subreg4_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
   "WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
@@ -2640,13 +2640,13 @@ (define_insn "*mov_si<mode>_e500_subreg4
    stw%U0%X0 %1,%0")
 
 (define_insn "*mov_si<mode>_e500_subreg4_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))]
   "!WORDS_BIG_ENDIAN
    && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
        || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
   "@
-   evmergehi %0,%0,%1
+   evmergelohi %0,%1,%1
    evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
   [(set_attr "length" "4,8")])
 
@@ -2668,16 +2668,16 @@ (define_insn "*mov_sitf_e500_subreg8_le"
    lwz%U1%X1 %L0,%1")
 
 (define_insn "*mov_sitf_e500_subreg8_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
   "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
-   evmergehi %0,%0,%L1
+   evmergelohi %0,%L1,%L1
    evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
   [(set_attr "length" "4,8")])
 
 (define_insn "*mov_sitf_e500_subreg8_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))]
   "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
@@ -2702,7 +2702,7 @@ (define_insn "*mov_sitf_e500_subreg12_le
   [(set_attr "length" "4,12")])
 
 (define_insn "*mov_sitf_e500_subreg12_2_be"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
   "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
@@ -2710,11 +2710,11 @@ (define_insn "*mov_sitf_e500_subreg12_2_
    stw%U0%X0 %L1,%0")
 
 (define_insn "*mov_sitf_e500_subreg12_2_le"
-  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
+  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
 	(subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))]
   "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
   "@
-   evmergehi %0,%0,%L1
+   evmergelohi %0,%L1,%L1
    evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
   [(set_attr "length" "4,8")])
 
