diff mbox series

rs6000: Put CR0 first in REG_ALLOC_ORDER

Message ID b0323d2a160894b6d08400fbbc5f41928bcc30c6.1539962409.git.segher@kernel.crashing.org
State New
Headers show
Series rs6000: Put CR0 first in REG_ALLOC_ORDER | expand

Commit Message

Segher Boessenkool Oct. 19, 2018, 3:35 p.m. UTC
IRA and LRA prefer to use CR7 (which is first in REG_ALLOC_ORDER) over
CR0, although the latter often is cheaper ("x" vs. "y" constraints).
We should figure out why this is and fix it; but until that is done,
this patch makes CR0 the first allocated register: it improves the
current code, and it is required for later patches to be effective.

(It changes two testcases to no longer look at what CR field is
allocated).

Committing to trunk.


2018-10-19  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.h (REG_ALLOC_ORDER): Move 68 (that is, CR0) to
	be the first CR field allocated.

gcc/testsuite/
	* gcc.target/powerpc/safe-indirect-jump-2.c: Do not check assigned CR
	field number.
	* gcc.target/powerpc/safe-indirect-jump-3.c: Ditto.

---
 gcc/config/rs6000/rs6000.h                              | 2 +-
 gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c | 6 ++----
 gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c | 6 ++----
 3 files changed, 5 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index eddb834..785e414 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -951,7 +951,7 @@  enum data_align { align_abi, align_opt, align_both };
    33,								\
    63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,		\
    50, 49, 48, 47, 46,						\
-   75, 73, 74, 69, 68, 72, 71, 70,				\
+   68, 75, 73, 74, 69, 72, 71, 70,				\
    MAYBE_R2_AVAILABLE						\
    9, 10, 8, 7, 6, 5, 4,					\
    3, EARLY_R12 11, 0,						\
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
index d3d040f..d6fc6a3 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
@@ -27,8 +27,6 @@  int foo (int x)
   return spaz (x) / 2;
 }
 
-/* The following assumes CR7 as the first chosen volatile.  */
-
-/* { dg-final { scan-assembler "crset 30" } } */
-/* { dg-final { scan-assembler "beqctr- 7" } } */
+/* { dg-final { scan-assembler "crset" } } */
+/* { dg-final { scan-assembler "beqctr-" } } */
 /* { dg-final { scan-assembler {b \$} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
index c338e30..87881fb 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
@@ -46,8 +46,6 @@  int foo (int x)
   return a;
 }
 
-/* The following assumes CR7 as the first chosen volatile.  */
-
-/* { dg-final { scan-assembler "crset 30" } } */
-/* { dg-final { scan-assembler "beqctr- 7" } } */
+/* { dg-final { scan-assembler "crset" } } */
+/* { dg-final { scan-assembler "beqctr-" } } */
 /* { dg-final { scan-assembler {b \$} } } */