From patchwork Fri Oct 19 15:35:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 986849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487902-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cJRvXvOo"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42c9356f26z9sDn for ; Sat, 20 Oct 2018 02:35:12 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=ZRzQeRSqNRbS lcTPYDPm3LU9GdfbYeCARvGLq/GA1W3XWlzE4Ywl7BahKLM+RhLAOJ57PbrtzDg1 baeWtU43NzrnaW6T3mW4RY/hrVyXjXm2pYxeDSfu1SzfsNmkk/X8sPpfUAE9AuG2 4bU3RGBwk/zL+v1UktX422Ued9pT00c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=3SVS4bgHOQdz3CWu9K R2Zvra2gw=; b=cJRvXvOoCawrMRkowLNKTpinh5gJAMfKANQfqe41ai/MZr5cve Rh+bc2VAJxa1dfKKCu88vaz21RJNQNvnluhLZXEM3xbDihFFvqthhMrs1nB98Bw9 iL4xs62GmAUiZyUDWgCyf4vBx046DSYT8DlNxvmU0eQEI0KHuq/Vxf/KY= Received: (qmail 69760 invoked by alias); 19 Oct 2018 15:35:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 69732 invoked by uid 89); 19 Oct 2018 15:35:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY autolearn=ham version=3.3.2 spammy=cheaper, Hx-languages-length:2785 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 19 Oct 2018 15:35:04 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 2BEF8124088B; Fri, 19 Oct 2018 15:35:02 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH] rs6000: Put CR0 first in REG_ALLOC_ORDER Date: Fri, 19 Oct 2018 15:35:00 +0000 Message-Id: X-IsSubscribed: yes IRA and LRA prefer to use CR7 (which is first in REG_ALLOC_ORDER) over CR0, although the latter often is cheaper ("x" vs. "y" constraints). We should figure out why this is and fix it; but until that is done, this patch makes CR0 the first allocated register: it improves the current code, and it is required for later patches to be effective. (It changes two testcases to no longer look at what CR field is allocated). Committing to trunk. 2018-10-19 Segher Boessenkool * config/rs6000/rs6000.h (REG_ALLOC_ORDER): Move 68 (that is, CR0) to be the first CR field allocated. gcc/testsuite/ * gcc.target/powerpc/safe-indirect-jump-2.c: Do not check assigned CR field number. * gcc.target/powerpc/safe-indirect-jump-3.c: Ditto. --- gcc/config/rs6000/rs6000.h | 2 +- gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c | 6 ++---- gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c | 6 ++---- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index eddb834..785e414 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -951,7 +951,7 @@ enum data_align { align_abi, align_opt, align_both }; 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ - 75, 73, 74, 69, 68, 72, 71, 70, \ + 68, 75, 73, 74, 69, 72, 71, 70, \ MAYBE_R2_AVAILABLE \ 9, 10, 8, 7, 6, 5, 4, \ 3, EARLY_R12 11, 0, \ diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c index d3d040f..d6fc6a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c +++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c @@ -27,8 +27,6 @@ int foo (int x) return spaz (x) / 2; } -/* The following assumes CR7 as the first chosen volatile. */ - -/* { dg-final { scan-assembler "crset 30" } } */ -/* { dg-final { scan-assembler "beqctr- 7" } } */ +/* { dg-final { scan-assembler "crset" } } */ +/* { dg-final { scan-assembler "beqctr-" } } */ /* { dg-final { scan-assembler {b \$} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c index c338e30..87881fb 100644 --- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c +++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c @@ -46,8 +46,6 @@ int foo (int x) return a; } -/* The following assumes CR7 as the first chosen volatile. */ - -/* { dg-final { scan-assembler "crset 30" } } */ -/* { dg-final { scan-assembler "beqctr- 7" } } */ +/* { dg-final { scan-assembler "crset" } } */ +/* { dg-final { scan-assembler "beqctr-" } } */ /* { dg-final { scan-assembler {b \$} } } */