| Message ID | alpine.LFD.2.21.2011200251040.656242@eddie.linux-mips.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | VAX: Bring the port up to date (yes, MODE_CC conversion is included) | expand |
On 11/19/20 8:35 PM, Maciej W. Rozycki wrote: > Our `ffssi2_internal' pattern and the machine FFS instruction, which > technically is a bitfield operation, match the `ctz' operation exactly, > with the result produced for the bitfield source operand of zero equal > to its width as specified with another machine instruction operand, not > directly expressed in RTL and currently hardcoded in the assembly code > produced. In our terms this is the bit size of the machine mode used, > and although it's SImode now let's be flexible for an upcoming change. > > The operation also sets the Z condition code according to the value of > the source operand. > > gcc/ > * config/vax/builtins.md (ffssi2_internal): Rename insn to... > (ctzsi2): ... this. Update the RTL operation. > (ffssi2): Update accordingly. > * gcc/config/vax/vax.c (vax_notice_update_cc): Handle CTZ. > * gcc/config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro. > > gcc/testsuite/ > * gcc.target/vax/ctzsi.c: New test. OK jeff
diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index 7e27854a8b0..e8cefe70d25 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -39,7 +39,7 @@ (define_expand "ffssi2" rtx cond = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx); rtx target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label_ref, pc_rtx); - emit_insn (gen_ffssi2_internal (operands[0], operands[1])); + emit_insn (gen_ctzsi2 (operands[0], operands[1])); emit_jump_insn (gen_rtx_SET (pc_rtx, target)); emit_insn (gen_negsi2 (operands[0], const1_rtx)); emit_label (label); @@ -47,9 +47,9 @@ (define_expand "ffssi2" DONE; }") -(define_insn "ffssi2_internal" +(define_insn "ctzsi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=rQ") - (ffs:SI (match_operand:SI 1 "general_operand" "nrQT"))) + (ctz:SI (match_operand:SI 1 "general_operand" "nrQT"))) (set (cc0) (compare (match_dup 1) (const_int 0)))] diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index b6c2210ca6b..69a05b33e95 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -1135,6 +1135,9 @@ vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED) case REG: cc_status.flags = CC_NO_OVERFLOW; break; + case CTZ: + cc_status.flags = CC_NOT_NEGATIVE; + break; default: break; } diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 146b0a6e2b2..43182ff1d88 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -683,3 +683,7 @@ VAX operand formatting codes: by the proper FDE definition. */ #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PC_REGNUM) +/* Upon failure to find the bit the FFS hardware instruction returns + the position of the bit immediately following the field specified. */ +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_BITSIZE (MODE), 2) diff --git a/gcc/testsuite/gcc.target/vax/ctzsi.c b/gcc/testsuite/gcc.target/vax/ctzsi.c new file mode 100644 index 00000000000..8be42712c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/vax/ctzsi.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ + +int +ctzsi (unsigned int x) +{ + return __builtin_ctz (x); +} + +/* Expect assembly like: + + ffs $0,$32,4(%ap),%r0 + + */ + +/* { dg-final { scan-assembler "\tffs \\\$0,\\\$32," } } */