From patchwork Fri Nov 20 03:35:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 1403453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux-mips.org Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CchyQ369tz9sSs for ; Fri, 20 Nov 2020 14:35:26 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4F60C395B801; Fri, 20 Nov 2020 03:35:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cvs.linux-mips.org (eddie.linux-mips.org [148.251.95.138]) by sourceware.org (Postfix) with ESMTP id E8D333959E4D for ; Fri, 20 Nov 2020 03:35:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E8D333959E4D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux-mips.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=macro@linux-mips.org Received: from localhost.localdomain ([127.0.0.1]:41578 "EHLO localhost" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23992241AbgKTDfVnz77y (ORCPT ); Fri, 20 Nov 2020 04:35:21 +0100 Date: Fri, 20 Nov 2020 03:35:21 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH 15/31] VAX: Provide the `ctz' operation In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anders Magnusson Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Our `ffssi2_internal' pattern and the machine FFS instruction, which technically is a bitfield operation, match the `ctz' operation exactly, with the result produced for the bitfield source operand of zero equal to its width as specified with another machine instruction operand, not directly expressed in RTL and currently hardcoded in the assembly code produced. In our terms this is the bit size of the machine mode used, and although it's SImode now let's be flexible for an upcoming change. The operation also sets the Z condition code according to the value of the source operand. gcc/ * config/vax/builtins.md (ffssi2_internal): Rename insn to... (ctzsi2): ... this. Update the RTL operation. (ffssi2): Update accordingly. * gcc/config/vax/vax.c (vax_notice_update_cc): Handle CTZ. * gcc/config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro. gcc/testsuite/ * gcc.target/vax/ctzsi.c: New test. --- gcc/config/vax/builtins.md | 6 +++--- gcc/config/vax/vax.c | 3 +++ gcc/config/vax/vax.h | 4 ++++ gcc/testsuite/gcc.target/vax/ctzsi.c | 15 +++++++++++++++ 4 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/vax/ctzsi.c diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index 7e27854a8b0..e8cefe70d25 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -39,7 +39,7 @@ (define_expand "ffssi2" rtx cond = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx); rtx target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label_ref, pc_rtx); - emit_insn (gen_ffssi2_internal (operands[0], operands[1])); + emit_insn (gen_ctzsi2 (operands[0], operands[1])); emit_jump_insn (gen_rtx_SET (pc_rtx, target)); emit_insn (gen_negsi2 (operands[0], const1_rtx)); emit_label (label); @@ -47,9 +47,9 @@ (define_expand "ffssi2" DONE; }") -(define_insn "ffssi2_internal" +(define_insn "ctzsi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=rQ") - (ffs:SI (match_operand:SI 1 "general_operand" "nrQT"))) + (ctz:SI (match_operand:SI 1 "general_operand" "nrQT"))) (set (cc0) (compare (match_dup 1) (const_int 0)))] diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index b6c2210ca6b..69a05b33e95 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -1135,6 +1135,9 @@ vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED) case REG: cc_status.flags = CC_NO_OVERFLOW; break; + case CTZ: + cc_status.flags = CC_NOT_NEGATIVE; + break; default: break; } diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 146b0a6e2b2..43182ff1d88 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -683,3 +683,7 @@ VAX operand formatting codes: by the proper FDE definition. */ #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PC_REGNUM) +/* Upon failure to find the bit the FFS hardware instruction returns + the position of the bit immediately following the field specified. */ +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_BITSIZE (MODE), 2) diff --git a/gcc/testsuite/gcc.target/vax/ctzsi.c b/gcc/testsuite/gcc.target/vax/ctzsi.c new file mode 100644 index 00000000000..8be42712c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/vax/ctzsi.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ + +int +ctzsi (unsigned int x) +{ + return __builtin_ctz (x); +} + +/* Expect assembly like: + + ffs $0,$32,4(%ap),%r0 + + */ + +/* { dg-final { scan-assembler "\tffs \\\$0,\\\$32," } } */