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[AArch64] Fix Prefetch ICE

Message ID SN2PR0701MB10247570E03A560AE426D37F8E4F0@SN2PR0701MB1024.namprd07.prod.outlook.com
State New
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Commit Message

Hurugalawadi, Naveen Sept. 28, 2015, 5:27 a.m. UTC 
Hi Marcus,

Thanks for the review and comments.

>> OK and can you back port to 5 ?

Please find attached the backported patch on gcc-5-branch.

Regression tested on AArch64 without any issues.

2015-09-28  Andrew Pinski  <apinski@cavium.com>    

ChangeLog

	* config/aarch64/aarch64.md (prefetch):
	Change the predicate of operand 0 to register_operand.

Thanks,
Naveen

Comments

Marcus Shawcroft Sept. 29, 2015, 8:30 a.m. UTC | #1 
On 28 September 2015 at 06:27, Hurugalawadi, Naveen
<Naveen.Hurugalawadi@caviumnetworks.com> wrote:
> Hi Marcus,
>
> Thanks for the review and comments.
>
>>> OK and can you back port to 5 ?
>
> Please find attached the backported patch on gcc-5-branch.
>
> Regression tested on AArch64 without any issues.
>
> 2015-09-28  Andrew Pinski  <apinski@cavium.com>
>
> ChangeLog
>
>         * config/aarch64/aarch64.md (prefetch):
>         Change the predicate of operand 0 to register_operand.

Thank you, please commit it if you have not already.
/M
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Patch

Index: config/aarch64/aarch64.md
===================================================================
--- config/aarch64/aarch64.md	(revision 228182)
+++ config/aarch64/aarch64.md	(working copy)
@@ -382,7 +382,7 @@ 
 )
 
 (define_insn "prefetch"
-  [(prefetch (match_operand:DI 0 "address_operand" "r")
+  [(prefetch (match_operand:DI 0 "register_operand" "r")
             (match_operand:QI 1 "const_int_operand" "")
             (match_operand:QI 2 "const_int_operand" ""))]
   ""