| Message ID | 20240603030953.3333366-4-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 | expand |
LGTM. Thanks. juzhe.zhong@rivai.ai From: pan2.li Date: 2024-06-03 11:09 To: gcc-patches CC: juzhe.zhong; kito.cheng; Pan Li Subject: [PATCH v1 4/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 From: Pan Li <pan2.li@intel.com> After the middle-end support the form 4 of unsigned SAT_ADD and the RISC-V backend implement the scalar .SAT_ADD, add more test case to cover the form 4 of unsigned .SAT_ADD. Form 4: #define SAT_ADD_U_4(T) \ T sat_add_u_4_##T (T x, T y) \ { \ T ret; \ return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test macro for form 4. * gcc.target/riscv/sat_u_add-17.c: New test. * gcc.target/riscv/sat_u_add-18.c: New test. * gcc.target/riscv/sat_u_add-19.c: New test. * gcc.target/riscv/sat_u_add-20.c: New test. * gcc.target/riscv/sat_u_add-run-17.c: New test. * gcc.target/riscv/sat_u_add-run-18.c: New test. * gcc.target/riscv/sat_u_add-run-19.c: New test. * gcc.target/riscv/sat_u_add-run-20.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-17.c | 19 ++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-18.c | 21 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-19.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-20.c | 17 +++++++++++++ .../gcc.target/riscv/sat_u_add-run-17.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add-run-18.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add-run-19.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_add-run-20.c | 25 +++++++++++++++++++ 9 files changed, 183 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index adb8be5886e..6ca158d57c4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -34,6 +34,13 @@ sat_u_add_##T##_fmt_4 (T x, T y) \ return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } +#define DEF_SAT_U_ADD_FMT_5(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_5 (T x, T y) \ +{ \ + T ret; \ + return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ +} #define DEF_VEC_SAT_U_ADD_FMT_1(T) \ void __attribute__((noinline)) \ @@ -52,6 +59,7 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) +#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c new file mode 100644 index 00000000000..7085ac835f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint8_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c new file mode 100644 index 00000000000..355ff8ba4ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint16_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c new file mode 100644 index 00000000000..491909165dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_fmt_5: +** addw\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c new file mode 100644 index 00000000000..c5f005cfe2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c new file mode 100644 index 00000000000..936028cbe8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c new file mode 100644 index 00000000000..a1d5d70b4ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c new file mode 100644 index 00000000000..7608e71dd80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c new file mode 100644 index 00000000000..496ab58150b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + +#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index adb8be5886e..6ca158d57c4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -34,6 +34,13 @@ sat_u_add_##T##_fmt_4 (T x, T y) \ return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } +#define DEF_SAT_U_ADD_FMT_5(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_5 (T x, T y) \ +{ \ + T ret; \ + return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ +} #define DEF_VEC_SAT_U_ADD_FMT_1(T) \ void __attribute__((noinline)) \ @@ -52,6 +59,7 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) +#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c new file mode 100644 index 00000000000..7085ac835f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-17.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint8_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c new file mode 100644 index 00000000000..355ff8ba4ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-18.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint16_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c new file mode 100644 index 00000000000..491909165dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_fmt_5: +** addw\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c new file mode 100644 index 00000000000..c5f005cfe2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_fmt_5: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_ADD_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c new file mode 100644 index 00000000000..936028cbe8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-17.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c new file mode 100644 index 00000000000..a1d5d70b4ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-18.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c new file mode 100644 index 00000000000..7608e71dd80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-19.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c new file mode 100644 index 00000000000..496ab58150b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-20.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 + +DEF_SAT_U_ADD_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + +#include "scalar_sat_binary.h"