Show patches with: Submitter = Li, Pan2       |    State = Action Required       |    Archived = No       |   907 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v1,4/4] RISC-V: Add more test cases for vwmacc[u].vv RISC-V: Allow RVV register overlap for vwmacc[u].vv - - - - --- 2026-08-12 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vwmaccu.vv reg overlap RISC-V: Allow RVV register overlap for vwmacc[u].vv - - - - --- 2026-08-12 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vwmacc.vv reg overlap RISC-V: Allow RVV register overlap for vwmacc[u].vv - - - - --- 2026-08-12 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vwmacc[u].vv RISC-V: Allow RVV register overlap for vwmacc[u].vv - - - - --- 2026-08-12 Li, Pan2 New
[v1,3/3] RISC-V: Add more test cases for vwmulsu.vv Support RVV register overlap for vwmulsu.vv - - - - --- 2026-08-05 Li, Pan2 New
[v1,2/3] RISC-V: Add test cases for vwmulsu.vv reg overlap Support RVV register overlap for vwmulsu.vv - - - - --- 2026-08-05 Li, Pan2 New
[v1,1/3] RISC-V: Allow RVV register overlap for vwmulsu.vv Support RVV register overlap for vwmulsu.vv - - - - --- 2026-08-05 Li, Pan2 New
[v1,5/5] RISC-V: Add more test cases for vwsub/vwsubu/vwmul/vwmulu.vv Add test cases for v[sub|mul][u].vv register overlap - - - - --- 2026-08-02 Li, Pan2 New
[v1,4/5] RISC-V: Add test cases for vwmulu.vv reg overlap Add test cases for v[sub|mul][u].vv register overlap - - - - --- 2026-08-02 Li, Pan2 New
[v1,3/5] RISC-V: Add test cases for vwmul.vv reg overlap Add test cases for v[sub|mul][u].vv register overlap - - - - --- 2026-08-02 Li, Pan2 New
[v1,2/5] RISC-V: Add test cases for vwsubu.vv reg overlap Add test cases for v[sub|mul][u].vv register overlap - - - - --- 2026-08-02 Li, Pan2 New
[v1,1/5] RISC-V: Add test cases for vwsub.vv reg overlap Add test cases for v[sub|mul][u].vv register overlap - - - - --- 2026-08-02 Li, Pan2 New
[v1,4/4] RISC-V: Add one more test case for vwadd.vv Support RVV register overlap for vwadd[u].vv - - - - --- 2026-07-31 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vwaddu.vv reg overlap Support RVV register overlap for vwadd[u].vv - - - - --- 2026-07-31 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vwadd.vv reg overlap Support RVV register overlap for vwadd[u].vv - - - - --- 2026-07-31 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vw{add, sub, mul}[u].vv Support RVV register overlap for vwadd[u].vv - - - - --- 2026-07-31 Li, Pan2 New
[v1,4/4] RISC-V: Add one more test case for vwsub.wv Support RVV register overlap for vwsub[u].wv - - - - --- 2026-07-28 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vwsubu.wv reg overlap Support RVV register overlap for vwsub[u].wv - - - - --- 2026-07-28 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vwsub.wv reg overlap Support RVV register overlap for vwsub[u].wv - - - - --- 2026-07-28 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vwsub[u].wv Support RVV register overlap for vwsub[u].wv - - - - --- 2026-07-28 Li, Pan2 New
[v1,4/4] RISC-V: Adjust test case due to allow vwadd[u].wv overlap Support RVV register overlap for vwadd[u].wv - - - - --- 2026-07-24 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vwaddu.wv reg overlap Support RVV register overlap for vwadd[u].wv - - - - --- 2026-07-24 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vwadd.wv reg overlap Support RVV register overlap for vwadd[u].wv - - - - --- 2026-07-24 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vwadd[u].wv Support RVV register overlap for vwadd[u].wv - - - - --- 2026-07-24 Li, Pan2 New
[v1,4/4] RISC-V: Adjust test case due to allow vwcvt.x[u].f.v overlap Support RVV register overlap for vfwcvt.rtz.x[u].f.v - - - - --- 2026-07-22 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vfwcvt.rtz.xu.f.v reg overlap Support RVV register overlap for vfwcvt.rtz.x[u].f.v - - - - --- 2026-07-22 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vfwcvt.rtz.x.f.v reg overlap Support RVV register overlap for vfwcvt.rtz.x[u].f.v - - - - --- 2026-07-22 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vfwcvt.rtz.x[u].f.v Support RVV register overlap for vfwcvt.rtz.x[u].f.v - - - - --- 2026-07-22 Li, Pan2 New
[v1,4/4] RISC-V: Adjust test case due to allow vwcvt.f.x[u].v overlap Support RVV register overlap for vfwcvt.f.x[u].v - - - - --- 2026-07-20 Li, Pan2 New
[v1,3/4] RISC-V: Adjust test case due to allow vwcvt.f.xu.v overlap Support RVV register overlap for vfwcvt.f.x[u].v - - - - --- 2026-07-20 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vfwcvt.f.x.v reg overlap Support RVV register overlap for vfwcvt.f.x[u].v - - - - --- 2026-07-20 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vfwcvt.f.x[u] Support RVV register overlap for vfwcvt.f.x[u].v - - - - --- 2026-07-20 Li, Pan2 New
[v1,3/3] RISC-V: Adjust test case due to allow vwcvt.f.f.v overlap Support RVV register overlap for vfwcvt.f.f.v - - - - --- 2026-07-19 Li, Pan2 New
[v1,2/3] RISC-V: Add test cases for vfwcvt.f.f.v reg overlap Support RVV register overlap for vfwcvt.f.f.v - - - - --- 2026-07-19 Li, Pan2 New
[v1,1/3] RISC-V: Allow RVV register overlap for vfwcvt.f.f.v Support RVV register overlap for vfwcvt.f.f.v - - - - --- 2026-07-19 Li, Pan2 New
[v1] RISC-V: Split the pr112431-13 test in to 2 file [v1] RISC-V: Split the pr112431-13 test in to 2 file - - - - --- 2026-07-18 Li, Pan2 New
[v1,3/3] RISC-V: Add test cases for vfwcvtu.xu.f.v reg overlap Support RVV register overlap for vfwcvt.x[u].f.v - - - - --- 2026-07-16 Li, Pan2 New
[v1,2/3] RISC-V: Add test cases for vfcvt.x.f.v reg overlap Support RVV register overlap for vfwcvt.x[u].f.v - - - - --- 2026-07-16 Li, Pan2 New
[v1,1/3] RISC-V: Allow RVV register overlap for vfwcvt.x[u].f.v Support RVV register overlap for vfwcvt.x[u].f.v - - - - --- 2026-07-16 Li, Pan2 New
[v1,4/4] RISC-V: Adjust test case due to allow vwcvt[u].x.x.v overlap Support RVV register overlap for vwcvt[u].x.x.v - - - - --- 2026-07-15 Li, Pan2 New
[v1,3/4] RISC-V: Add test cases for vwcvtu.x.x.v reg overlap Support RVV register overlap for vwcvt[u].x.x.v - - - - --- 2026-07-15 Li, Pan2 New
[v1,2/4] RISC-V: Add test cases for vwcvt.x.x.v reg overlap Support RVV register overlap for vwcvt[u].x.x.v - - - - --- 2026-07-15 Li, Pan2 New
[v1,1/4] RISC-V: Allow RVV register overlap for vwcvt[u].x.x.v Support RVV register overlap for vwcvt[u].x.x.v - - - - --- 2026-07-15 Li, Pan2 New
[v1,5/5] RISC-V: Adjust test case due to allow vf[sz]ext.vf8 overlap Support RVV register overlap for v[sz]ext.vf8 - - - - --- 2026-07-12 Li, Pan2 New
[v1,4/5] RISC-V: Adjust the scan asm for v[sz]ext.vf2 for v[123] Support RVV register overlap for v[sz]ext.vf8 - - - - --- 2026-07-12 Li, Pan2 New
[v1,3/5] RISC-V: Add test cases for vzext.vf8 reg overlap Support RVV register overlap for v[sz]ext.vf8 - - - - --- 2026-07-12 Li, Pan2 New
[v1,2/5] RISC-V: Add test cases for vsext.vf8 reg overlap Support RVV register overlap for v[sz]ext.vf8 - - - - --- 2026-07-12 Li, Pan2 New
[v1,1/5] RISC-V: Allow RVV register overlap for v[sz]ext.vf8 Support RVV register overlap for v[sz]ext.vf8 - - - - --- 2026-07-12 Li, Pan2 New
[v1,5/5] RISC-V: Adjust test case due to vf[sz]ext.vf4 overlap Support RVV register overlap for v[sz]ext.vf4 - - - - --- 2026-07-08 Li, Pan2 New
[v1,4/5] RISC-V: Adjust the scan asm for v[sz]ext.vf2 for v1 and v12 Support RVV register overlap for v[sz]ext.vf4 - - - - --- 2026-07-08 Li, Pan2 New
[v1,3/5] RISC-V: Add test cases for vzext.vf4 reg overlap Support RVV register overlap for v[sz]ext.vf4 - - - - --- 2026-07-08 Li, Pan2 New
[v1,2/5] RISC-V: Add test cases for vsext.vf4 reg overlap Support RVV register overlap for v[sz]ext.vf4 - - - - --- 2026-07-08 Li, Pan2 New
[v1,1/5] RISC-V: Allow RVV register overlap for v[sz]ext.vf4 Support RVV register overlap for v[sz]ext.vf4 - - - - --- 2026-07-08 Li, Pan2 New
[v2,3/3] RISC-V: Add test cases for vzext.vf2 reg overlap Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-07 Li, Pan2 New
[v2,2/3] RISC-V: Add test cases for vsext.vf2 reg overlap Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-07 Li, Pan2 New
[v2,1/3] RISC-V: Allow RVV register overlap for v[sz]ext.vf2 Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-07 Li, Pan2 New
[v1,3/3] RISC-V: Add test cases for vzext.vf2 reg overlap Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-03 Li, Pan2 New
[v1,2/3] RISC-V: Add test cases for vsext.vf2 reg overlap Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-03 Li, Pan2 New
[v1,1/3] RISC-V: Allow RVV register overlap for v[sz]ext.vf2 Support RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-07-03 Li, Pan2 New
[v1,4/4] RISC-V: Add testcase for unsigned scalar SAT_MUL form 19 Add test for unsigned scalar SAT_MUL form 16-19 - - - - --- 2026-06-30 Li, Pan2 New
[v1,3/4] RISC-V: Add testcase for unsigned scalar SAT_MUL form 18 Add test for unsigned scalar SAT_MUL form 16-19 - - - - --- 2026-06-30 Li, Pan2 New
[v1,2/4] RISC-V: Add testcase for unsigned scalar SAT_MUL form 17 Add test for unsigned scalar SAT_MUL form 16-19 - - - - --- 2026-06-30 Li, Pan2 New
[v1,1/4] RISC-V: Add testcase for unsigned scalar SAT_MUL form 16 Add test for unsigned scalar SAT_MUL form 16-19 - - - - --- 2026-06-30 Li, Pan2 New
[WIP] RISC-V: Allow RVV register overlap for v[sz]ext.vf2 [WIP] RISC-V: Allow RVV register overlap for v[sz]ext.vf2 - - - - --- 2026-06-29 Li, Pan2 New
[v1,3/3] RISC-V: Add testcase for unsigned scalar SAT_MUL form 15 Implement unsigned scalar SAT_MUL form 14 - - - - --- 2026-06-24 Li, Pan2 New
[v1,2/3] RISC-V: Add testcase for unsigned scalar SAT_MUL form 14 Implement unsigned scalar SAT_MUL form 14 - - - - --- 2026-06-24 Li, Pan2 New
[v1,1/3] Match: Support unsigned scalar SAT_MUL form 14 Implement unsigned scalar SAT_MUL form 14 - - - - --- 2026-06-24 Li, Pan2 New
[v2,3/3] RISC-V: Add testcase for unsigned scalar SAT_MUL form 13 Implement unsigned scalar SAT_MUL form 13 - - - - --- 2026-06-18 Li, Pan2 New
[v2,2/3] Match: Ensure call to tree_to_uhwi is checked in SAT_* pattern(s) Implement unsigned scalar SAT_MUL form 13 - - - - --- 2026-06-18 Li, Pan2 New
[v2,1/3] Match: Support unsigned scalar SAT_MUL form 13 Implement unsigned scalar SAT_MUL form 13 - - - - --- 2026-06-18 Li, Pan2 New
[v1,2/2] RISC-V: Add testcase for unsigned scalar SAT_MUL form 13 Implement unsigned scalar SAT_MUL form 13 - - - - --- 2026-06-16 Li, Pan2 New
[v1,1/2] Match: Support unsigned scalar SAT_MUL form 13 Implement unsigned scalar SAT_MUL form 13 - - - - --- 2026-06-16 Li, Pan2 New
[v1] RISC-V: Add testcase for unsigned scalar SAT_MUL form 12 [v1] RISC-V: Add testcase for unsigned scalar SAT_MUL form 12 - - - - --- 2026-06-04 Li, Pan2 New
[v1,2/2] RISC-V: Add testcase for unsigned scalar SAT_MUL form 11 Implement unsigned scalar SAT_MUL form 11 - - - - --- 2026-05-19 Li, Pan2 New
[v1,1/2] Match: Support unsigned scalar SAT_MUL form 11 Implement unsigned scalar SAT_MUL form 11 - - - - --- 2026-05-19 Li, Pan2 New
[v1,3/3] RISC-V: Add test cases for scalar unsigned SAT form 10 Add test cases for scalar unsigned SAT_MUL form 8, 9, 10 - - - - --- 2026-05-13 Li, Pan2 New
[v1,2/3] RISC-V: Add test cases for scalar unsigned SAT form 9 Add test cases for scalar unsigned SAT_MUL form 8, 9, 10 - - - - --- 2026-05-13 Li, Pan2 New
[v1,1/3] RISC-V: Add test cases for scalar unsigned SAT form 8 Add test cases for scalar unsigned SAT_MUL form 8, 9, 10 - - - - --- 2026-05-13 Li, Pan2 New
[v2] Match: Move saturation alu patterns into match-sat-alu.pd [NFC] [v2] Match: Move saturation alu patterns into match-sat-alu.pd [NFC] - - - - --- 2026-05-08 Li, Pan2 New
[v1] Match: Move saturation alu patterns into match-sat-alu.pd [NFC] [v1] Match: Move saturation alu patterns into match-sat-alu.pd [NFC] - - - - --- 2026-05-08 Li, Pan2 New
[v1,2/2] RISC-V: Add test for vec_duplicate + vmsgt.vv combine with GR2VR cost 0, 1 and 15 RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost - - - - --- 2026-05-06 Li, Pan2 New
[v1,1/2] RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost - - - - --- 2026-05-06 Li, Pan2 New
[v1,2/2] RISC-V: Add test for vec_duplicate + vmsgtu.vv combine with GR2VR cost 0, 1 and 15 RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost - - - - --- 2026-04-28 Li, Pan2 New
[v1,1/2] RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost - - - - --- 2026-04-28 Li, Pan2 New
[v1,3/3] RISC-V: Add test cases for v[zs]ext.vf2 reg overlap for m2 Allow reg overlap of v[sz]ext.vf2 for m2 - - - - --- 2026-02-26 Li, Pan2 New
[v1,2/3] RISC-V: Adjust the testcase due to overlap change. Allow reg overlap of v[sz]ext.vf2 for m2 - - - - --- 2026-02-26 Li, Pan2 New
[v1,1/3] RISC-V: Allow RVV reg overlap of v[sz]ext.vf2 for m2 Allow reg overlap of v[sz]ext.vf2 for m2 - - - - --- 2026-02-26 Li, Pan2 New
[v1] RISC-V: Add another combine pattern for vfmin/max on cost model [v1] RISC-V: Add another combine pattern for vfmin/max on cost model - - - - --- 2026-02-17 Li, Pan2 New
[v1,6/6] RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c [PR123916] Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,5/6] RISC-V: Add test case for PR123916 Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,4/6] RISC-V: Adjust the vf-[378]* testcase by param=vr2fpr-cost [PR123916] Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,3/6] RISC-V: Introduce vr2fpr-cost= for customizing the cost when vr2fpr [PR123916] Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,2/6] RISC-V: Adjust the vx-[456]* testcase by param=vr2gpr-cost [PR123916] Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,1/6] RISC-V: Introduce vr2gpr-cost= for customizing the cost when vr2gpr [PR123916] Add vr2gpr and vr2fpr cost value param - - - - --- 2026-02-04 Li, Pan2 New
[v1,2/2] RISC-V: Add test case for PR123916 Bugfix adjust_stmt_cost doesn't honor param=gpr2vr-cost - - - - --- 2026-02-02 Li, Pan2 New
[v1,1/2] RISC-V: Bugfix adjust_stmt_cost doesn't honor param=gpr2vr-cost [PR123916] Bugfix adjust_stmt_cost doesn't honor param=gpr2vr-cost - - - - --- 2026-02-02 Li, Pan2 New
[v1,2/2] RISC-V: Add test for vec_duplicate + vmsle.vv combine with GR2VR cost 0, 1 and 15 RISC-V: Combine vec_duplicate + vmsle.vv to vmsle.vx on GR2VR cost - - - - --- 2026-01-13 Li, Pan2 New
[v1,1/2] RISC-V: Combine vec_duplicate + vmsle.vv to vmsle.vx on GR2VR cost RISC-V: Combine vec_duplicate + vmsle.vv to vmsle.vx on GR2VR cost - - - - --- 2026-01-13 Li, Pan2 New
[v1,2/2] RISC-V: Add run test case for vwadd/vwsub wx mis combine [PR123317] Fix incorrect combine pattern for vwaddu/vwsubu wx - - - - --- 2026-01-05 Li, Pan2 New
[v1,1/2] RISC-V: Fix incorrect combine pattern for any_extend [PR123317] Fix incorrect combine pattern for vwaddu/vwsubu wx - - - - --- 2026-01-05 Li, Pan2 New
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