| Message ID | 20240514231316.25967-2-palmer@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Implement -m{,no}fence-tso | expand |
On 5/14/24 5:13 PM, Palmer Dabbelt wrote: > Some processors from T-Head don't implement the `fence.tso` instruction > natively and instead trap to firmware. This breaks some users who > haven't yet updated the firmware and one could imagine it breaking users > who are trying to build firmware if they're using the C memory model. > > So just add an option to disable emitting it, in a similar fashion to > how we allow users to forbid other instructions. > > gcc/ChangeLog: > > * config/riscv/riscv.opt: Add -mno-fence-tso. > * config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect > -mno-fence-tso. > * doc/invoke.texi (RISC-V): Document -mno-fence-tso. > > Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959 > --- > I've just smoke tested this one, but > > void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); } > > generates `fence.tso` without the argument and `fence rw,rw` with > `-mno-fence-tso`, so it seems to be at least mostly there. I figured > I'd just send it up for comments before putting together the DG bits: > it's kind of a pain to carry around these workarounds for unimplemented > instructions, but it's in HW so there's not much we can do about that. Seems reasonable. We might consider adding a comment in the code indicating this is for a particular set of thead systems. 10 years from now when someone else looks at the code they'll know why this is in there and they won't have to do the archaeology. Jeff
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 1252834aec5..fb8dac3df80 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -622,3 +622,7 @@ Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) mtls-dialect= Target RejectNegative Joined Enum(tls_type) Var(riscv_tls_dialect) Init(TLS_TRADITIONAL) Save Specify TLS dialect. + +mfence-tso +Target Var(TARGET_FENCE_TSO) Init(1) +Specifies whether the fence.tso instruction should be used. diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index d4fd26069f7..e639a1e2392 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -33,7 +33,7 @@ (define_insn "mem_thread_fence_rvwmo" if (model == MEMMODEL_SEQ_CST) return "fence\trw,rw"; else if (model == MEMMODEL_ACQ_REL) - return "fence.tso"; + return TARGET_FENCE_TSO ? "fence.tso" : "fence\trw,rw"; else if (model == MEMMODEL_ACQUIRE) return "fence\tr,rw"; else if (model == MEMMODEL_RELEASE) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ddcd5213f06..90b329b674b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1243,6 +1243,7 @@ See RS/6000 and PowerPC Options. -mplt -mno-plt -mabi=@var{ABI-string} -mfdiv -mno-fdiv +-mfence-tso -mno-fence-tso -mdiv -mno-div -misa-spec=@var{ISA-spec-string} -march=@var{ISA-string} @@ -30384,6 +30385,13 @@ Do or don't use hardware floating-point divide and square root instructions. This requires the F or D extensions for floating-point registers. The default is to use them if the specified architecture has these instructions. +@opindex mfence-tso +@item -mfence-tso +@itemx -mno-fence-tso +Do or don't use the @samp{fence.tso} instruction, which is unimplemented on +some processors (including those from T-Head). If the @samp{fence.tso} +instruction is not availiable then a stronger fence will be used instead. + @opindex mdiv @item -mdiv @itemx -mno-div
Some processors from T-Head don't implement the `fence.tso` instruction natively and instead trap to firmware. This breaks some users who haven't yet updated the firmware and one could imagine it breaking users who are trying to build firmware if they're using the C memory model. So just add an option to disable emitting it, in a similar fashion to how we allow users to forbid other instructions. gcc/ChangeLog: * config/riscv/riscv.opt: Add -mno-fence-tso. * config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect -mno-fence-tso. * doc/invoke.texi (RISC-V): Document -mno-fence-tso. Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959 --- I've just smoke tested this one, but void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); } generates `fence.tso` without the argument and `fence rw,rw` with `-mno-fence-tso`, so it seems to be at least mostly there. I figured I'd just send it up for comments before putting together the DG bits: it's kind of a pain to carry around these workarounds for unimplemented instructions, but it's in HW so there's not much we can do about that. --- gcc/config/riscv/riscv.opt | 4 ++++ gcc/config/riscv/sync-rvwmo.md | 2 +- gcc/doc/invoke.texi | 8 ++++++++ 3 files changed, 13 insertions(+), 1 deletion(-)