| Message ID | 20240228041625.1469884-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV | expand |
Keep SCALABLE, since it has different semantics with ZVL: -mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN -mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN What's difference exactly? -mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128 -mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with VLEN == 128 Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b Give more practical example on codegen with clang: https://godbolt.org/z/vhdnGvK37 So it more like alias of --param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable. On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote: > > From: Pan Li <pan2.li@intel.com> > > This patch would like to introduce one new gcc option for RVV. To > appoint the bits size of one RVV vector register. Valid arguments to > '-mrvv-vector-bits=' are: > > * zvl > > The zvl will pick up the zvl*b from the march option. For example, > the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b. > > The below test are passed for this patch. > > * The riscv fully regression test. > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for > different RVV vector bits. > * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to > get the RVV vector bits, with given min_vlen. > (riscv_convert_vector_chunks): Combine the mrvv-vector-bits > option with min_vlen to RVV vector chunks. > (riscv_override_options_internal): Update comments and rename the > vector chunks. > * config/riscv/riscv.opt: Add option mrvv-vector-bits. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. > > Signed-off-by: Pan Li <pan2.li@intel.com> > --- > gcc/config/riscv/riscv-opts.h | 7 +++++ > gcc/config/riscv/riscv.cc | 31 +++++++++++++++---- > gcc/config/riscv/riscv.opt | 11 +++++++ > .../riscv/rvv/base/rvv-vector-bits-1.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-2.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-3.c | 25 +++++++++++++++ > 6 files changed, 82 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 4edddbadc37..0162e00515b 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum { > VSETVL_OPT_NO_FUSION, > }; > > +/* RVV vector bits for option -mrvv-vector-bits > + zvl indicates take the bits of zvl*b provided by march as vector bits. > + */ > +enum rvv_vector_bits_enum { > + RVV_VECTOR_BITS_ZVL, > +}; > + > #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) > > /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 5e984ee2a55..d18e5226bce 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void) > return ggc_cleared_alloc<machine_function> (); > } > > -/* Return the VLEN value associated with -march. > +static int > +riscv_convert_vector_bits (int min_vlen) > +{ > + int rvv_bits = 0; > + > + switch (rvv_vector_bits) > + { > + case RVV_VECTOR_BITS_ZVL: > + rvv_bits = min_vlen; > + break; > + default: > + gcc_unreachable (); > + } > + > + return rvv_bits; > +} > + > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. > TODO: So far we only support length-agnostic value. */ > static poly_uint16 > -riscv_convert_vector_bits (struct gcc_options *opts) > +riscv_convert_vector_chunks (struct gcc_options *opts) > { > int chunk_num; > int min_vlen = TARGET_MIN_VLEN_OPTS (opts); > + int rvv_bits = riscv_convert_vector_bits (min_vlen); > + > if (min_vlen > 32) > { > /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. > @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > - TARGET_MIN_VLEN = 2048bit: [256,256] > - TARGET_MIN_VLEN = 4096bit: [512,512] > FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */ > - chunk_num = min_vlen / 64; > + chunk_num = rvv_bits / 64; > } > else > { > @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > if (TARGET_VECTOR_OPTS_P (opts)) > { > if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) > - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); > + return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8); > else > return poly_uint16 (chunk_num, chunk_num); > } > @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts) > if (TARGET_VECTOR && TARGET_BIG_ENDIAN) > sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); > > - /* Convert -march to a chunks count. */ > - riscv_vector_chunks = riscv_convert_vector_bits (opts); > + /* Convert -march and -mrvv-vector-bits to a chunks count. */ > + riscv_vector_chunks = riscv_convert_vector_chunks (opts); > } > > /* Implement TARGET_OPTION_OVERRIDE. */ > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 20685c42aed..42ea8efd05d 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) > mstringop-strategy= > Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) > Specify stringop expansion strategy. > + > +Enum > +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) > +The possible RVV vector register lengths: > + > +EnumValue > +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) > + > +mrvv-vector-bits= > +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL) > +-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector register. > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > new file mode 100644 > index 00000000000..24bc4211cde > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > new file mode 100644 > index 00000000000..f4f8ff6a6fb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > new file mode 100644 > index 00000000000..962cc8ffa6d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > @@ -0,0 +1,25 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +/* > +** test_rvv_vector_bits_zvl: > +** ... > +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ... > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ret > +** ... > +*/ > +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) > +{ > + for (int i = 0; i < 8; i++) > + out[i] = a[i] + b[i]; > +} > -- > 2.34.1 >
Oh, I see, that indicates simply convert this option value to riscv_vector_chunks is not good enough here. I thought the term zvl* indicates the minimal vector length(somehow similar to the concept of scalable) in previous, which is mentioned in the RVV 1.0 spec if my memory is correct. Looks march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I will update it in v3 accordingly for the difference semantics here. Pan -----Original Message----- From: Kito Cheng <kito.cheng@gmail.com> Sent: Wednesday, February 28, 2024 2:17 PM To: Li, Pan2 <pan2.li@intel.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com Subject: Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Keep SCALABLE, since it has different semantics with ZVL: -mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN -mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN What's difference exactly? -mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128 -mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with VLEN == 128 Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b Give more practical example on codegen with clang: https://godbolt.org/z/vhdnGvK37 So it more like alias of --param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable. On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote: > > From: Pan Li <pan2.li@intel.com> > > This patch would like to introduce one new gcc option for RVV. To > appoint the bits size of one RVV vector register. Valid arguments to > '-mrvv-vector-bits=' are: > > * zvl > > The zvl will pick up the zvl*b from the march option. For example, > the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b. > > The below test are passed for this patch. > > * The riscv fully regression test. > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for > different RVV vector bits. > * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to > get the RVV vector bits, with given min_vlen. > (riscv_convert_vector_chunks): Combine the mrvv-vector-bits > option with min_vlen to RVV vector chunks. > (riscv_override_options_internal): Update comments and rename the > vector chunks. > * config/riscv/riscv.opt: Add option mrvv-vector-bits. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. > > Signed-off-by: Pan Li <pan2.li@intel.com> > --- > gcc/config/riscv/riscv-opts.h | 7 +++++ > gcc/config/riscv/riscv.cc | 31 +++++++++++++++---- > gcc/config/riscv/riscv.opt | 11 +++++++ > .../riscv/rvv/base/rvv-vector-bits-1.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-2.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-3.c | 25 +++++++++++++++ > 6 files changed, 82 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 4edddbadc37..0162e00515b 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum { > VSETVL_OPT_NO_FUSION, > }; > > +/* RVV vector bits for option -mrvv-vector-bits > + zvl indicates take the bits of zvl*b provided by march as vector bits. > + */ > +enum rvv_vector_bits_enum { > + RVV_VECTOR_BITS_ZVL, > +}; > + > #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) > > /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 5e984ee2a55..d18e5226bce 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void) > return ggc_cleared_alloc<machine_function> (); > } > > -/* Return the VLEN value associated with -march. > +static int > +riscv_convert_vector_bits (int min_vlen) > +{ > + int rvv_bits = 0; > + > + switch (rvv_vector_bits) > + { > + case RVV_VECTOR_BITS_ZVL: > + rvv_bits = min_vlen; > + break; > + default: > + gcc_unreachable (); > + } > + > + return rvv_bits; > +} > + > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. > TODO: So far we only support length-agnostic value. */ > static poly_uint16 > -riscv_convert_vector_bits (struct gcc_options *opts) > +riscv_convert_vector_chunks (struct gcc_options *opts) > { > int chunk_num; > int min_vlen = TARGET_MIN_VLEN_OPTS (opts); > + int rvv_bits = riscv_convert_vector_bits (min_vlen); > + > if (min_vlen > 32) > { > /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. > @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > - TARGET_MIN_VLEN = 2048bit: [256,256] > - TARGET_MIN_VLEN = 4096bit: [512,512] > FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */ > - chunk_num = min_vlen / 64; > + chunk_num = rvv_bits / 64; > } > else > { > @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > if (TARGET_VECTOR_OPTS_P (opts)) > { > if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) > - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); > + return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8); > else > return poly_uint16 (chunk_num, chunk_num); > } > @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts) > if (TARGET_VECTOR && TARGET_BIG_ENDIAN) > sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); > > - /* Convert -march to a chunks count. */ > - riscv_vector_chunks = riscv_convert_vector_bits (opts); > + /* Convert -march and -mrvv-vector-bits to a chunks count. */ > + riscv_vector_chunks = riscv_convert_vector_chunks (opts); > } > > /* Implement TARGET_OPTION_OVERRIDE. */ > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 20685c42aed..42ea8efd05d 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) > mstringop-strategy= > Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) > Specify stringop expansion strategy. > + > +Enum > +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) > +The possible RVV vector register lengths: > + > +EnumValue > +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) > + > +mrvv-vector-bits= > +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL) > +-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector register. > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > new file mode 100644 > index 00000000000..24bc4211cde > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > new file mode 100644 > index 00000000000..f4f8ff6a6fb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > new file mode 100644 > index 00000000000..962cc8ffa6d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > @@ -0,0 +1,25 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +/* > +** test_rvv_vector_bits_zvl: > +** ... > +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ... > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ret > +** ... > +*/ > +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) > +{ > + for (int i = 0; i < 8; i++) > + out[i] = a[i] + b[i]; > +} > -- > 2.34.1 >
Updated in v3, please help to continue review below link. Sorry for sending another v3 by mistake. https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646734.html Pan -----Original Message----- From: Li, Pan2 Sent: Wednesday, February 28, 2024 2:33 PM To: Kito Cheng <kito.cheng@gmail.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com Subject: RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Oh, I see, that indicates simply convert this option value to riscv_vector_chunks is not good enough here. I thought the term zvl* indicates the minimal vector length(somehow similar to the concept of scalable) in previous, which is mentioned in the RVV 1.0 spec if my memory is correct. Looks march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I will update it in v3 accordingly for the difference semantics here. Pan -----Original Message----- From: Kito Cheng <kito.cheng@gmail.com> Sent: Wednesday, February 28, 2024 2:17 PM To: Li, Pan2 <pan2.li@intel.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com Subject: Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Keep SCALABLE, since it has different semantics with ZVL: -mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN -mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN What's difference exactly? -mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128 -mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with VLEN == 128 Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b Give more practical example on codegen with clang: https://godbolt.org/z/vhdnGvK37 So it more like alias of --param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable. On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote: > > From: Pan Li <pan2.li@intel.com> > > This patch would like to introduce one new gcc option for RVV. To > appoint the bits size of one RVV vector register. Valid arguments to > '-mrvv-vector-bits=' are: > > * zvl > > The zvl will pick up the zvl*b from the march option. For example, > the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b. > > The below test are passed for this patch. > > * The riscv fully regression test. > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for > different RVV vector bits. > * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to > get the RVV vector bits, with given min_vlen. > (riscv_convert_vector_chunks): Combine the mrvv-vector-bits > option with min_vlen to RVV vector chunks. > (riscv_override_options_internal): Update comments and rename the > vector chunks. > * config/riscv/riscv.opt: Add option mrvv-vector-bits. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. > * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. > > Signed-off-by: Pan Li <pan2.li@intel.com> > --- > gcc/config/riscv/riscv-opts.h | 7 +++++ > gcc/config/riscv/riscv.cc | 31 +++++++++++++++---- > gcc/config/riscv/riscv.opt | 11 +++++++ > .../riscv/rvv/base/rvv-vector-bits-1.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-2.c | 7 +++++ > .../riscv/rvv/base/rvv-vector-bits-3.c | 25 +++++++++++++++ > 6 files changed, 82 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 4edddbadc37..0162e00515b 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum { > VSETVL_OPT_NO_FUSION, > }; > > +/* RVV vector bits for option -mrvv-vector-bits > + zvl indicates take the bits of zvl*b provided by march as vector bits. > + */ > +enum rvv_vector_bits_enum { > + RVV_VECTOR_BITS_ZVL, > +}; > + > #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) > > /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 5e984ee2a55..d18e5226bce 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void) > return ggc_cleared_alloc<machine_function> (); > } > > -/* Return the VLEN value associated with -march. > +static int > +riscv_convert_vector_bits (int min_vlen) > +{ > + int rvv_bits = 0; > + > + switch (rvv_vector_bits) > + { > + case RVV_VECTOR_BITS_ZVL: > + rvv_bits = min_vlen; > + break; > + default: > + gcc_unreachable (); > + } > + > + return rvv_bits; > +} > + > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. > TODO: So far we only support length-agnostic value. */ > static poly_uint16 > -riscv_convert_vector_bits (struct gcc_options *opts) > +riscv_convert_vector_chunks (struct gcc_options *opts) > { > int chunk_num; > int min_vlen = TARGET_MIN_VLEN_OPTS (opts); > + int rvv_bits = riscv_convert_vector_bits (min_vlen); > + > if (min_vlen > 32) > { > /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. > @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > - TARGET_MIN_VLEN = 2048bit: [256,256] > - TARGET_MIN_VLEN = 4096bit: [512,512] > FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */ > - chunk_num = min_vlen / 64; > + chunk_num = rvv_bits / 64; > } > else > { > @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) > if (TARGET_VECTOR_OPTS_P (opts)) > { > if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) > - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); > + return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8); > else > return poly_uint16 (chunk_num, chunk_num); > } > @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts) > if (TARGET_VECTOR && TARGET_BIG_ENDIAN) > sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); > > - /* Convert -march to a chunks count. */ > - riscv_vector_chunks = riscv_convert_vector_bits (opts); > + /* Convert -march and -mrvv-vector-bits to a chunks count. */ > + riscv_vector_chunks = riscv_convert_vector_chunks (opts); > } > > /* Implement TARGET_OPTION_OVERRIDE. */ > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 20685c42aed..42ea8efd05d 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) > mstringop-strategy= > Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) > Specify stringop expansion strategy. > + > +Enum > +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) > +The possible RVV vector register lengths: > + > +EnumValue > +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) > + > +mrvv-vector-bits= > +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL) > +-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector register. > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > new file mode 100644 > index 00000000000..24bc4211cde > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > new file mode 100644 > index 00000000000..f4f8ff6a6fb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ > + > +#include "riscv_vector.h" > + > +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ > +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > new file mode 100644 > index 00000000000..962cc8ffa6d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c > @@ -0,0 +1,25 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +/* > +** test_rvv_vector_bits_zvl: > +** ... > +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ... > +** vle32\.v\s+v[0-9]+,\s*0\(a0\) > +** vle32\.v\s+v[0-9]+,\s*0\(a1\) > +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ > +** vse32\.v\s+v[0-9]+,\s*0\(a2\) > +** ret > +** ... > +*/ > +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) > +{ > + for (int i = 0; i < 8; i++) > + out[i] = a[i] + b[i]; > +} > -- > 2.34.1 >
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4edddbadc37..0162e00515b 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum { VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits + zvl indicates take the bits of zvl*b provided by march as vector bits. + */ +enum rvv_vector_bits_enum { + RVV_VECTOR_BITS_ZVL, +}; + #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5e984ee2a55..d18e5226bce 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void) return ggc_cleared_alloc<machine_function> (); } -/* Return the VLEN value associated with -march. +static int +riscv_convert_vector_bits (int min_vlen) +{ + int rvv_bits = 0; + + switch (rvv_vector_bits) + { + case RVV_VECTOR_BITS_ZVL: + rvv_bits = min_vlen; + break; + default: + gcc_unreachable (); + } + + return rvv_bits; +} + +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. TODO: So far we only support length-agnostic value. */ static poly_uint16 -riscv_convert_vector_bits (struct gcc_options *opts) +riscv_convert_vector_chunks (struct gcc_options *opts) { int chunk_num; int min_vlen = TARGET_MIN_VLEN_OPTS (opts); + int rvv_bits = riscv_convert_vector_bits (min_vlen); + if (min_vlen > 32) { /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) - TARGET_MIN_VLEN = 2048bit: [256,256] - TARGET_MIN_VLEN = 4096bit: [512,512] FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */ - chunk_num = min_vlen / 64; + chunk_num = rvv_bits / 64; } else { @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) if (TARGET_VECTOR_OPTS_P (opts)) { if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); + return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8); else return poly_uint16 (chunk_num, chunk_num); } @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts) if (TARGET_VECTOR && TARGET_BIG_ENDIAN) sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); - /* Convert -march to a chunks count. */ - riscv_vector_chunks = riscv_convert_vector_bits (opts); + /* Convert -march and -mrvv-vector-bits to a chunks count. */ + riscv_vector_chunks = riscv_convert_vector_chunks (opts); } /* Implement TARGET_OPTION_OVERRIDE. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 20685c42aed..42ea8efd05d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy. + +Enum +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) +The possible RVV vector register lengths: + +EnumValue +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) + +mrvv-vector-bits= +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL) +-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector register. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c new file mode 100644 index 00000000000..24bc4211cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c new file mode 100644 index 00000000000..f4f8ff6a6fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c new file mode 100644 index 00000000000..962cc8ffa6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** test_rvv_vector_bits_zvl: +** ... +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma +** vle32\.v\s+v[0-9]+,\s*0\(a0\) +** vle32\.v\s+v[0-9]+,\s*0\(a1\) +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse32\.v\s+v[0-9]+,\s*0\(a2\) +** ... +** vle32\.v\s+v[0-9]+,\s*0\(a0\) +** vle32\.v\s+v[0-9]+,\s*0\(a1\) +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse32\.v\s+v[0-9]+,\s*0\(a2\) +** ret +** ... +*/ +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) +{ + for (int i = 0; i < 8; i++) + out[i] = a[i] + b[i]; +}