| Message ID | 20240226045352.736663-1-gkm@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: add option -m(no-)autovec-segment | expand |
On 2/25/24 21:53, Greg McGary wrote: > Add option -m(no-)autovec-segment to enable/disable autovectorizer > from emitting vector segment load/store instructions. This is useful for > performance experiments. > > gcc/ChangeLog: > * config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes): > Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT > * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro. > * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. > * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero. > * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, > testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. I don't mind having options to do this kind of selection (we've done similar things internally for other RVV features). But I don't think now is the time to be introducing this stuff. We're in stage4 of the development cycle after all. jeff
On 2/27/24 8:25 AM, Jeff Law wrote: > > > On 2/25/24 21:53, Greg McGary wrote: >> Add option -m(no-)autovec-segment to enable/disable autovectorizer >> from emitting vector segment load/store instructions. This is useful for >> performance experiments. >> >> gcc/ChangeLog: >> * config/riscv/autovec.md (vec_mask_len_load_lanes, >> vec_mask_len_store_lanes): >> Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT >> * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): >> New macro. >> * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. >> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent >> divide-by-zero. >> * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, >> testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. > I don't mind having options to do this kind of selection (we've done > similar things internally for other RVV features). But I don't think > now is the time to be introducing this stuff. We're in stage4 of the > development cycle after all. No problemo. Will you take the simple bugfix? gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero. diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index 1dbe1115da4..6303d82d959 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo, - (vec_num * j + i) * nunits); /* remain should now be > 0 and < nunits. */ unsigned num; - if (constant_multiple_p (nunits, remain, &num)) + if (known_gt (remain, 0) + && constant_multiple_p (nunits, remain, &num)) { tree ptype; new_vtype I am unaware of a testcase that triggers it without disabling segmented load, so LMK if you are cool with the fix without a test case. G
On 2/27/24 13:30, Greg McGary wrote: > On 2/27/24 8:25 AM, Jeff Law wrote: > >> >> >> On 2/25/24 21:53, Greg McGary wrote: >>> Add option -m(no-)autovec-segment to enable/disable autovectorizer >>> from emitting vector segment load/store instructions. This is useful for >>> performance experiments. >>> >>> gcc/ChangeLog: >>> * config/riscv/autovec.md (vec_mask_len_load_lanes, >>> vec_mask_len_store_lanes): >>> Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT >>> * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): >>> New macro. >>> * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. >>> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent >>> divide-by-zero. >>> * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, >>> testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. >> I don't mind having options to do this kind of selection (we've done >> similar things internally for other RVV features). But I don't think >> now is the time to be introducing this stuff. We're in stage4 of the >> development cycle after all. > > > No problemo. Will you take the simple bugfix? > > gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero. > diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc > > index 1dbe1115da4..6303d82d959 100644 > --- a/gcc/tree-vect-stmts.cc > +++ b/gcc/tree-vect-stmts.cc > @@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo, > - (vec_num * j + i) * nunits); > /* remain should now be > 0 and < nunits. */ > unsigned num; > - if (constant_multiple_p (nunits, remain, &num)) > + if (known_gt (remain, 0) > + && constant_multiple_p (nunits, remain, &num)) > { > tree ptype; > new_vtype > > > I am unaware of a testcase that triggers it without disabling segmented > load, so LMK if you are cool with the fix without a test case. We'd really need a testcase and some analysis -- this change will affect every target, so you'd need to explain why the change is correct. jeff
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3b32369f68c..d43d1f7852a 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -282,7 +282,7 @@ (match_operand:<VM> 2 "vector_mask_operand") (match_operand 3 "autovec_length_operand") (match_operand 4 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR_AUTOVEC_SEGMENT" { riscv_vector::expand_lanes_load_store (operands, true); DONE; @@ -295,7 +295,7 @@ (match_operand:<VM> 2 "vector_mask_operand") (match_operand 3 "autovec_length_operand") (match_operand 4 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR_AUTOVEC_SEGMENT" { riscv_vector::expand_lanes_load_store (operands, false); DONE; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4edddbadc37..ca924968a79 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -152,4 +152,9 @@ enum vsetvl_strategy_enum { #define TARGET_MAX_LMUL \ (int) (riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul) +/* On some microarchitectures, vector segment loads and stores are excessively + expensive, so predicate the generation of those instrunctions. */ +#define TARGET_VECTOR_AUTOVEC_SEGMENT \ + (TARGET_VECTOR && riscv_mautovec_segment) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 20685c42aed..05a021423a0 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -607,3 +607,7 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy. + +mautovec-segment +Target Integer Var(riscv_mautovec_segment) Init(1) +Enable (default) or disable generation of vector segment load/store instructions. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c new file mode 100644 index 00000000000..b0feccf853f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -mno-autovec-segment" } */ + +enum e { c, d }; +enum g { f }; + +struct h +{ + float x, w; +}; + +struct k +{ + short z, y, i, j; +}; + +long r; +struct h m, p; +struct k *q; + +short +l (float s) +{ + if (s <= 0.0f) + return 0; + + if (s >= 5) + return 5; + + return s; +} + +struct n +{ + enum g colorspace; +}; + +struct n o (struct k *s, struct h *t) +{ + t->w = s->z; +} + +void +ClutImageChannel (struct n *s, enum e t) +{ + + while (s) + for (; r; r++) + { + o (q, &p); + + if (t & d) + q->y = (&m + q->y)->x; + + if (t) + q->z = l ((&m + q->z)->w); + + if (s->colorspace) + q++; + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c new file mode 100644 index 00000000000..277761263f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c new file mode 100644 index 00000000000..addeba0033d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c new file mode 100644 index 00000000000..c02cff002f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c new file mode 100644 index 00000000000..7b4be34bcf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c new file mode 100644 index 00000000000..0f999187dd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c new file mode 100644 index 00000000000..5dc550b9206 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c new file mode 100644 index 00000000000..761b47e61e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c new file mode 100644 index 00000000000..072359548eb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c new file mode 100644 index 00000000000..7118ea38927 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c new file mode 100644 index 00000000000..38608f56475 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c new file mode 100644 index 00000000000..5e565fd2e44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c new file mode 100644 index 00000000000..8bcaa2e340a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c new file mode 100644 index 00000000000..8328962fcbe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c new file mode 100644 index 00000000000..db2a5cf908c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c new file mode 100644 index 00000000000..c7415ec86f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c new file mode 100644 index 00000000000..f0abda66ef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c new file mode 100644 index 00000000000..4331c7bac13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c new file mode 100644 index 00000000000..599fbd78e02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c new file mode 100644 index 00000000000..1757b0e27b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c new file mode 100644 index 00000000000..0dea4f3300e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c new file mode 100644 index 00000000000..90b8432fbc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c new file mode 100644 index 00000000000..fcd9b0302a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c new file mode 100644 index 00000000000..5541a3a7105 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c new file mode 100644 index 00000000000..415d7cfd025 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c new file mode 100644 index 00000000000..e5471c2242f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c new file mode 100644 index 00000000000..178057f7724 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c new file mode 100644 index 00000000000..91e24d64aa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c new file mode 100644 index 00000000000..5ce8bb7bae2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c new file mode 100644 index 00000000000..8d040bd2535 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*16,\s*e8,\s*m1,\s*t[au],\s*m[au]} 8 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c new file mode 100644 index 00000000000..9f533f4ff49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-10.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c new file mode 100644 index 00000000000..2b12ed16822 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-11.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c new file mode 100644 index 00000000000..265e2905653 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-12.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c new file mode 100644 index 00000000000..ff134ecbbc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-13.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c new file mode 100644 index 00000000000..06648125073 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-14.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c new file mode 100644 index 00000000000..356054bf6a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-15.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c new file mode 100644 index 00000000000..21d36c002d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-16.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c new file mode 100644 index 00000000000..7f9763682a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-17.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c new file mode 100644 index 00000000000..86bdc2ca8d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-18.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c new file mode 100644 index 00000000000..24fc8c745ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*m1,\s*t[au],\s*m[au]} 8 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c new file mode 100644 index 00000000000..16f4fd366e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c new file mode 100644 index 00000000000..1d18033e174 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]} 46 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c new file mode 100644 index 00000000000..d5983ef95ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c new file mode 100644 index 00000000000..9b158b9b740 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c new file mode 100644 index 00000000000..d9495e77d7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c new file mode 100644 index 00000000000..5e239e8b934 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-8.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c new file mode 100644 index 00000000000..5248f2a39c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-9.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c new file mode 100644 index 00000000000..0e24c5772b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c new file mode 100644 index 00000000000..e095b769906 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c new file mode 100644 index 00000000000..549dd15ad22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c new file mode 100644 index 00000000000..8fa80cf6530 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c new file mode 100644 index 00000000000..9b0e3b7881d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c new file mode 100644 index 00000000000..34b871e7073 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c new file mode 100644 index 00000000000..4166903f11a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c new file mode 100644 index 00000000000..f86a3a7c6de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c new file mode 100644 index 00000000000..113c8c8fd72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c new file mode 100644 index 00000000000..a1436fab644 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c new file mode 100644 index 00000000000..2108b5e9592 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c new file mode 100644 index 00000000000..5640a7e66a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c new file mode 100644 index 00000000000..2bfda096552 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c new file mode 100644 index 00000000000..6c03a7caf3d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c new file mode 100644 index 00000000000..4d216ae197c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c new file mode 100644 index 00000000000..d1a00f1aed6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c new file mode 100644 index 00000000000..a0a35a90e3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c new file mode 100644 index 00000000000..286a7efe2fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-9.c" diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index 1dbe1115da4..6303d82d959 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo, - (vec_num * j + i) * nunits); /* remain should now be > 0 and < nunits. */ unsigned num; - if (constant_multiple_p (nunits, remain, &num)) + if (known_gt (remain, 0) + && constant_multiple_p (nunits, remain, &num)) { tree ptype; new_vtype