diff mbox series

[v1] RISC-V: Refine test cases for both PR112929 and PR112988

Message ID 20231213134927.3453856-1-pan2.li@intel.com
State New
Headers show
Series [v1] RISC-V: Refine test cases for both PR112929 and PR112988 | expand

Commit Message

Li, Pan2 Dec. 13, 2023, 1:49 p.m. UTC 
From: Pan Li <pan2.li@intel.com>

Refine the test cases for:

* Name convention.
* Add run case.

	PR target/112929
	PR target/112988

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr112929.c: Moved to...
	* gcc.target/riscv/rvv/vsetvl/pr112929-1.c: ...here.
	* gcc.target/riscv/rvv/vsetvl/pr112988.c: Moved to...
	* gcc.target/riscv/rvv/vsetvl/pr112988-1.c: ...here.
	* gcc.target/riscv/rvv/vsetvl/pr112929-2.c: New test.
	* gcc.target/riscv/rvv/vsetvl/pr112988-2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../rvv/vsetvl/{pr112929.c => pr112929-1.c}   |  0
 .../gcc.target/riscv/rvv/vsetvl/pr112929-2.c  | 57 +++++++++++++++++++
 .../rvv/vsetvl/{pr112988.c => pr112988-1.c}   |  0
 .../gcc.target/riscv/rvv/vsetvl/pr112988-2.c  | 53 +++++++++++++++++
 4 files changed, 110 insertions(+)
 rename gcc/testsuite/gcc.target/riscv/rvv/vsetvl/{pr112929.c => pr112929-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-2.c
 rename gcc/testsuite/gcc.target/riscv/rvv/vsetvl/{pr112988.c => pr112988-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-2.c

Comments

Robin Dapp Dec. 13, 2023, 1:55 p.m. UTC | #1 
Thanks, LGTM but please add a comment like:

These test cases used to cause out-of-bounds writes to the stack
and therefore showed unreliable behavior.  Depending on the
execution environment they can either pass or fail.  As of now,
with the latest QEMU version, they will pass even without the
underlying issue fixed.  As the test case is known to have
caused the problem before we keep it as a run test case for
future reference.

Regards
 Robin
Li, Pan2 Dec. 13, 2023, 2:09 p.m. UTC | #2 
Committed with below comments, thanks Juzhe and Robin.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Wednesday, December 13, 2023 9:56 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; juzhe.zhong@rivai.ai
Subject: Re: [PATCH v1] RISC-V: Refine test cases for both PR112929 and PR112988

Thanks, LGTM but please add a comment like:

These test cases used to cause out-of-bounds writes to the stack
and therefore showed unreliable behavior.  Depending on the
execution environment they can either pass or fail.  As of now,
with the latest QEMU version, they will pass even without the
underlying issue fixed.  As the test case is known to have
caused the problem before we keep it as a run test case for
future reference.

Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929.c
rename to gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-2.c
new file mode 100644
index 00000000000..f2022026639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-2.c
@@ -0,0 +1,57 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model" } */
+
+int printf(char *, ...);
+int a, l, i, p, q, t, n, o;
+int *volatile c;
+static int j;
+static struct pack_1_struct d;
+long e;
+char m = 5;
+short s;
+
+#pragma pack(1)
+struct pack_1_struct {
+  long c;
+  int d;
+  int e;
+  int f;
+  int g;
+  int h;
+  int i;
+} h, r = {1}, *f = &h, *volatile g;
+
+void add_em_up(int count, ...) {
+  __builtin_va_list ap;
+  __builtin_va_start(ap, count);
+  __builtin_va_end(ap);
+}
+
+int main() {
+  int u;
+  j = 0;
+
+  for (; j < 9; ++j) {
+    u = ++t ? a : 0;
+    if (u) {
+      int *v = &d.d;
+      *v = g || e;
+      *c = 0;
+      *f = h;
+    }
+    s = l && c;
+    o = i;
+    d.f || (p = 0);
+    q |= n;
+  }
+
+  r = *f;
+
+  add_em_up(1, 1);
+  printf("%d\n", m);
+
+  if (m != 5)
+    __builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988.c
rename to gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-2.c
new file mode 100644
index 00000000000..e952b85b630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-2.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model" } */
+
+int a = 0;
+int p, q, r, x = 230;
+short d;
+int e[256];
+static struct f w;
+int *c = &r;
+
+short y(short z) {
+  return z * d;
+}
+
+#pragma pack(1)
+struct f {
+  int g;
+  short h;
+  int j;
+  char k;
+  char l;
+  long m;
+  long n;
+  int o;
+} s = {1}, v, t, *u = &v, *b = &s;
+
+void add_em_up(int count, ...) {
+  __builtin_va_list ap;
+  __builtin_va_start(ap, count);
+  __builtin_va_end(ap);
+}
+
+int main() {
+  int i = 0;
+  for (; i < 256; i++)
+    e[i] = i;
+
+  p = 0;
+  for (; p <= 0; p++) {
+    *c = 4;
+    *u = t;
+    x |= y(6 >= q);
+  }
+
+  *b = w;
+
+  add_em_up(1, 1);
+
+  if (a != 0 || q != 0 || p != 1 || r != 4 || x != 0xE6 || d != 0)
+    __builtin_abort ();
+
+  return 0;
+}