diff mbox series

[3/5] aarch64: rcpc3: Add Neon ACLE intrinsics

Message ID 20231109141300.3542453-4-victor.donascimento@arm.com
State New
Headers show
Series aarch64: Add ACLE intrinsics codegen support for lrcpc3 instructions | expand

Commit Message

Victor Do Nascimento Nov. 9, 2023, 2:12 p.m. UTC 
Register the target specific builtins in `aarch64-simd-builtins.def'
and implement their associated backend patterns in `aarch64-simd.md'.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def
	(vec_ldap1_lane): New.
	(vec_stl1_lane): Likewise.
	* config/aarch64/aarch64-simd.md
	(aarch64_vec_stl1_lanes<mode>_lane<Vel>): New.
	(aarch64_vec_stl1_lane<mode>): Likewise.
	(aarch64_vec_ldap1_lanes<mode>_lane<Vel>): Likewise.
	(aarch64_vec_ldap1_lane<mode>): Likewise.
---
 gcc/config/aarch64/aarch64-simd-builtins.def |  7 +++
 gcc/config/aarch64/aarch64-simd.md           | 65 ++++++++++++++++++++
 gcc/config/aarch64/aarch64.md                |  2 +
 3 files changed, 74 insertions(+)

Comments

Richard Sandiford Nov. 24, 2023, 11:38 a.m. UTC | #1 
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Register the target specific builtins in `aarch64-simd-builtins.def'
> and implement their associated backend patterns in `aarch64-simd.md'.
>
> gcc/ChangeLog:
>
> 	* config/aarch64/aarch64-simd-builtins.def
> 	(vec_ldap1_lane): New.
> 	(vec_stl1_lane): Likewise.
> 	* config/aarch64/aarch64-simd.md
> 	(aarch64_vec_stl1_lanes<mode>_lane<Vel>): New.
> 	(aarch64_vec_stl1_lane<mode>): Likewise.
> 	(aarch64_vec_ldap1_lanes<mode>_lane<Vel>): Likewise.
> 	(aarch64_vec_ldap1_lane<mode>): Likewise.

OK, thanks.

Richard

> ---
>  gcc/config/aarch64/aarch64-simd-builtins.def |  7 +++
>  gcc/config/aarch64/aarch64-simd.md           | 65 ++++++++++++++++++++
>  gcc/config/aarch64/aarch64.md                |  2 +
>  3 files changed, 74 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
> index e2b94ad8247..0ae6c4ad41a 100644
> --- a/gcc/config/aarch64/aarch64-simd-builtins.def
> +++ b/gcc/config/aarch64/aarch64-simd-builtins.def
> @@ -43,6 +43,13 @@
>     help describe the attributes (for example, pure) for the intrinsic
>     function.  */
>  
> +  BUILTIN_V12DIF (LOADSTRUCT_LANE, vec_ldap1_lane, 0, ALL)
> +  BUILTIN_V12DIUP (LOADSTRUCT_LANE_U, vec_ldap1_lane, 0, ALL)
> +  BUILTIN_V12DIUP (LOADSTRUCT_LANE_P, vec_ldap1_lane, 0, ALL)
> +  BUILTIN_V12DIF (STORESTRUCT_LANE, vec_stl1_lane, 0, ALL)
> +  BUILTIN_V12DIUP (STORESTRUCT_LANE_U, vec_stl1_lane, 0, ALL)
> +  BUILTIN_V12DIUP (STORESTRUCT_LANE_P, vec_stl1_lane, 0, ALL)
> +
>    BUILTIN_VDC (BINOP, combine, 0, AUTO_FP)
>    BUILTIN_VD_I (BINOPU, combine, 0, NONE)
>    BUILTIN_VDC_P (BINOPP, combine, 0, NONE)
> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> index 81ff5bad03d..79697336f61 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -7697,6 +7697,71 @@
>    DONE;
>  })
>  
> +;; Patterns for rcpc3 vector lane loads and stores.
> +
> +(define_insn "aarch64_vec_stl1_lanes<mode>_lane<Vel>"
> +  [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Q")
> +	(unspec:BLK [(match_operand:V12DIF 1 "register_operand" "w")
> +		     (match_operand:SI 2 "immediate_operand" "i")]
> +		     UNSPEC_STL1_LANE))]
> +  "TARGET_RCPC3"
> +  {
> +    operands[2] = aarch64_endian_lane_rtx (<MODE>mode,
> +					   INTVAL (operands[2]));
> +    return "stl1\\t{%S1.<Vetype>}[%2], %0";
> +  }
> +  [(set_attr "type" "neon_store2_one_lane")]
> +)
> +
> +(define_expand "aarch64_vec_stl1_lane<mode>"
> + [(match_operand:DI 0 "register_operand")
> +  (match_operand:V12DIF 1 "register_operand")
> +  (match_operand:SI 2 "immediate_operand")]
> +  "TARGET_RCPC3"
> +{
> +  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
> +  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
> +
> +  aarch64_simd_lane_bounds (operands[2], 0,
> +			    GET_MODE_NUNITS (<MODE>mode).to_constant (), NULL);
> +  emit_insn (gen_aarch64_vec_stl1_lanes<mode>_lane<Vel> (mem,
> +					operands[1], operands[2]));
> +  DONE;
> +})
> +
> +(define_insn "aarch64_vec_ldap1_lanes<mode>_lane<Vel>"
> +  [(set (match_operand:V12DIF 0 "register_operand" "=w")
> +	(unspec:V12DIF [
> +		(match_operand:BLK 1 "aarch64_simd_struct_operand" "Q")
> +		(match_operand:V12DIF 2 "register_operand" "0")
> +		(match_operand:SI 3 "immediate_operand" "i")]
> +		UNSPEC_LDAP1_LANE))]
> +  "TARGET_RCPC3"
> +  {
> +    operands[3] = aarch64_endian_lane_rtx (<MODE>mode,
> +					   INTVAL (operands[3]));
> +    return "ldap1\\t{%S0.<Vetype>}[%3], %1";
> +  }
> +  [(set_attr "type" "neon_load2_one_lane")]
> +)
> +
> +(define_expand "aarch64_vec_ldap1_lane<mode>"
> +  [(match_operand:V12DIF 0 "register_operand")
> +	(match_operand:DI 1 "register_operand")
> +	(match_operand:V12DIF 2 "register_operand")
> +	(match_operand:SI 3 "immediate_operand")]
> +  "TARGET_RCPC3"
> +{
> +  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
> +  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
> +
> +  aarch64_simd_lane_bounds (operands[3], 0,
> +			    GET_MODE_NUNITS (<MODE>mode).to_constant (), NULL);
> +  emit_insn (gen_aarch64_vec_ldap1_lanes<mode>_lane<Vel> (operands[0],
> +				mem, operands[2], operands[3]));
> +  DONE;
> +})
> +
>  (define_insn_and_split "aarch64_rev_reglist<mode>"
>  [(set (match_operand:VSTRUCT_QD 0 "register_operand" "=&w")
>  	(unspec:VSTRUCT_QD
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 5bb8c772be8..fb6de3b1fbf 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -295,6 +295,8 @@
>      UNSPEC_LD1RO
>      UNSPEC_SALT_ADDR
>      UNSPECV_PATCHABLE_AREA
> +    UNSPEC_LDAP1_LANE
> +    UNSPEC_STL1_LANE
>  ])
>  
>  (define_c_enum "unspecv" [
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index e2b94ad8247..0ae6c4ad41a 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -43,6 +43,13 @@ 
    help describe the attributes (for example, pure) for the intrinsic
    function.  */
 
+  BUILTIN_V12DIF (LOADSTRUCT_LANE, vec_ldap1_lane, 0, ALL)
+  BUILTIN_V12DIUP (LOADSTRUCT_LANE_U, vec_ldap1_lane, 0, ALL)
+  BUILTIN_V12DIUP (LOADSTRUCT_LANE_P, vec_ldap1_lane, 0, ALL)
+  BUILTIN_V12DIF (STORESTRUCT_LANE, vec_stl1_lane, 0, ALL)
+  BUILTIN_V12DIUP (STORESTRUCT_LANE_U, vec_stl1_lane, 0, ALL)
+  BUILTIN_V12DIUP (STORESTRUCT_LANE_P, vec_stl1_lane, 0, ALL)
+
   BUILTIN_VDC (BINOP, combine, 0, AUTO_FP)
   BUILTIN_VD_I (BINOPU, combine, 0, NONE)
   BUILTIN_VDC_P (BINOPP, combine, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 81ff5bad03d..79697336f61 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7697,6 +7697,71 @@ 
   DONE;
 })
 
+;; Patterns for rcpc3 vector lane loads and stores.
+
+(define_insn "aarch64_vec_stl1_lanes<mode>_lane<Vel>"
+  [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Q")
+	(unspec:BLK [(match_operand:V12DIF 1 "register_operand" "w")
+		     (match_operand:SI 2 "immediate_operand" "i")]
+		     UNSPEC_STL1_LANE))]
+  "TARGET_RCPC3"
+  {
+    operands[2] = aarch64_endian_lane_rtx (<MODE>mode,
+					   INTVAL (operands[2]));
+    return "stl1\\t{%S1.<Vetype>}[%2], %0";
+  }
+  [(set_attr "type" "neon_store2_one_lane")]
+)
+
+(define_expand "aarch64_vec_stl1_lane<mode>"
+ [(match_operand:DI 0 "register_operand")
+  (match_operand:V12DIF 1 "register_operand")
+  (match_operand:SI 2 "immediate_operand")]
+  "TARGET_RCPC3"
+{
+  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
+
+  aarch64_simd_lane_bounds (operands[2], 0,
+			    GET_MODE_NUNITS (<MODE>mode).to_constant (), NULL);
+  emit_insn (gen_aarch64_vec_stl1_lanes<mode>_lane<Vel> (mem,
+					operands[1], operands[2]));
+  DONE;
+})
+
+(define_insn "aarch64_vec_ldap1_lanes<mode>_lane<Vel>"
+  [(set (match_operand:V12DIF 0 "register_operand" "=w")
+	(unspec:V12DIF [
+		(match_operand:BLK 1 "aarch64_simd_struct_operand" "Q")
+		(match_operand:V12DIF 2 "register_operand" "0")
+		(match_operand:SI 3 "immediate_operand" "i")]
+		UNSPEC_LDAP1_LANE))]
+  "TARGET_RCPC3"
+  {
+    operands[3] = aarch64_endian_lane_rtx (<MODE>mode,
+					   INTVAL (operands[3]));
+    return "ldap1\\t{%S0.<Vetype>}[%3], %1";
+  }
+  [(set_attr "type" "neon_load2_one_lane")]
+)
+
+(define_expand "aarch64_vec_ldap1_lane<mode>"
+  [(match_operand:V12DIF 0 "register_operand")
+	(match_operand:DI 1 "register_operand")
+	(match_operand:V12DIF 2 "register_operand")
+	(match_operand:SI 3 "immediate_operand")]
+  "TARGET_RCPC3"
+{
+  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
+
+  aarch64_simd_lane_bounds (operands[3], 0,
+			    GET_MODE_NUNITS (<MODE>mode).to_constant (), NULL);
+  emit_insn (gen_aarch64_vec_ldap1_lanes<mode>_lane<Vel> (operands[0],
+				mem, operands[2], operands[3]));
+  DONE;
+})
+
 (define_insn_and_split "aarch64_rev_reglist<mode>"
 [(set (match_operand:VSTRUCT_QD 0 "register_operand" "=&w")
 	(unspec:VSTRUCT_QD
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5bb8c772be8..fb6de3b1fbf 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -295,6 +295,8 @@ 
     UNSPEC_LD1RO
     UNSPEC_SALT_ADDR
     UNSPECV_PATCHABLE_AREA
+    UNSPEC_LDAP1_LANE
+    UNSPEC_STL1_LANE
 ])
 
 (define_c_enum "unspecv" [