| Message ID | 20230719101156.21771-2-zengxiao@eswincomputing.com |
|---|---|
| State | New |
| Headers | show |
| Series | Recognize Zicond extension | expand |
On 7/19/23 04:11, Xiao Zeng wrote: > This patch is the minimal support for Zicond extension, include > the extension name, mask and target defination. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: New extension. > * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. > (TARGET_ZICOND): New target. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/attribute-20.c: New test. > * gcc.target/riscv/attribute-21.c: New test. This is OK. Though I don't think we should install until the follow-on patches are ready to go. jeff
On 7/19/23 04:11, Xiao Zeng wrote: > This patch is the minimal support for Zicond extension, include > the extension name, mask and target defination. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: New extension. > * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. > (TARGET_ZICOND): New target. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/attribute-20.c: New test. > * gcc.target/riscv/attribute-21.c: New test. I've pushed this to the trunk. jeff
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 6091d8f281b..8460d83b0f1 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -183,6 +183,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1243,6 +1245,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cfcf608ea62..cecaee7d200 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -236,6 +236,9 @@ enum riscv_entity #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) +#define MASK_ZICOND (1 << 2) +#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0) + #define MASK_ZFHMIN (1 << 0) #define MASK_ZFH (1 << 1) #define MASK_ZVFHMIN (1 << 2) diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c new file mode 100644 index 00000000000..b69c36cf4f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zicond -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicond1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-21.c b/gcc/testsuite/gcc.target/riscv/attribute-21.c new file mode 100644 index 00000000000..160312a0d48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-21.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zicond -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicond1p0\"" } } */