diff mbox series

[v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

Message ID 20220209031837.3167330-1-yunqiang.su@cipunited.com
State New
Headers show
Series [v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU | expand

Commit Message

YunQiang Su Feb. 9, 2022, 3:18 a.m. UTC 
If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_expand_prologue):
	  IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jeff Law Feb. 12, 2022, 3:54 a.m. UTC | #1 
On 2/8/2022 8:18 PM, YunQiang Su wrote:
> If MIPS MCU extension is enable, the IPL section in Cause register
> has been expand to 8bit instead of 6bit.
>
> gcc/ChangeLog:
>
> 	* config/mips/mips.cc (mips_expand_prologue):
> 	  IPL is 8bit for MCU ASE.
OK
jeff
Maciej W. Rozycki Feb. 12, 2022, 8:47 a.m. UTC | #2 
On Fri, 11 Feb 2022, Jeff Law wrote:

> > If MIPS MCU extension is enable, the IPL section in Cause register
> > has been expand to 8bit instead of 6bit.
> > 
> > gcc/ChangeLog:
> > 
> > 	* config/mips/mips.cc (mips_expand_prologue):
> > 	  IPL is 8bit for MCU ASE.
> OK

 But this is still wrong AFAICT.

 The mask is applied to the CP0 Status register according to the comment, 
but the layout of the interrupt bit-field is different between the CP0 
Status and the CP0 Cause registers, so you can't just extract it from one 
of the two registers and directly apply to the other.

 I would like to know how this code has been verified.

  Maciej
YunQiang Su March 15, 2022, 7 a.m. UTC | #3 
在 2022/2/12 16:47, Maciej W. Rozycki 写道:
> On Fri, 11 Feb 2022, Jeff Law wrote:
> 
>>> If MIPS MCU extension is enable, the IPL section in Cause register
>>> has been expand to 8bit instead of 6bit.
>>>
>>> gcc/ChangeLog:
>>>
>>> 	* config/mips/mips.cc (mips_expand_prologue):
>>> 	  IPL is 8bit for MCU ASE.
>> OK
> 
>   But this is still wrong AFAICT.
> 

Yes. you are right.

>   The mask is applied to the CP0 Status register according to the comment,
> but the layout of the interrupt bit-field is different between the CP0
> Status and the CP0 Cause registers, so you can't just extract it from one
> of the two registers and directly apply to the other.
> 

Since our case has 128 interrupts, so I didn't find this problem.

>   I would like to know how this code has been verified.

And now new version sent with the test with 256 interrupts.

See v3 please.

> 
>    Maciej
> .
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..d823c459b75 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@  mips_expand_prologue (void)
 	      if (!cfun->machine->keep_interrupts_masked_p
 		  && cfun->machine->int_mask == INT_MASK_EIC)
 		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-				       GEN_INT (6),
+				       TARGET_MCU ? GEN_INT (8) : GEN_INT (6),
 				       GEN_INT (SR_IPL),
 				       gen_rtx_REG (SImode, K0_REG_NUM)));