| Message ID | 20210812040532.25854-1-hongtao.liu@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it. | expand |
On Thu, Aug 12, 2021 at 12:05 PM liuhongt <hongtao.liu@intel.com> wrote: > > Hi: > This is the patch i'm going to checkin. > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}; > > > 2021-08-12 Uros Bizjak <ubizjak@gmail.com> > > gcc/ChangeLog: > > PR target/98309 > * config/i386/i386.md (avx512f_scalef<mode>2): New > define_insn. > (ldexp<mode>3): Adjust for new define_insn. > (UNSPEC_SCALEF): Move from sse.md. > * config/i386/sse.md (UNSPEC_SCALEF): Move to i386.md. > --- > gcc/config/i386/i386.md | 27 +++++++++++++++++++-------- > gcc/config/i386/sse.md | 1 - > 2 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 56b09c566ed..4a8e8fea290 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -125,6 +125,9 @@ (define_c_enum "unspec" [ > UNSPEC_RSQRT > UNSPEC_PSADBW > > + ;; For AVX512F support > + UNSPEC_SCALEF > + > ;; Generic math support > UNSPEC_COPYSIGN > UNSPEC_XORSIGN > @@ -17894,6 +17897,17 @@ (define_expand "expm1<mode>2" > DONE; > }) > > +(define_insn "avx512f_scalef<mode>2" > + [(set (match_operand:MODEF 0 "register_operand" "=v") > + (unspec:MODEF > + [(match_operand:MODEF 1 "register_operand" "v") > + (match_operand:MODEF 2 "nonimmediate_operand" "vm")] > + UNSPEC_SCALEF))] > + "TARGET_AVX512F" > + "vscalef<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "prefix" "evex") > + (set_attr "mode" "<MODE>")]) > + > (define_expand "ldexpxf3" > [(match_operand:XF 0 "register_operand") > (match_operand:XF 1 "register_operand") > @@ -17924,15 +17938,12 @@ (define_expand "ldexp<mode>3" > if (TARGET_AVX512F && TARGET_SSE_MATH) > { > rtx op2 = gen_reg_rtx (<MODE>mode); > - emit_insn (gen_floatsi<mode>2 (op2, operands[2])); > - operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode); > - if (MEM_P (operands[1])) > + > + if (!nonimmediate_operand (operands[1], <MODE>mode)) > operands[1] = force_reg (<MODE>mode, operands[1]); > - operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode); > - op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode); > - emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0], > - operands[1], > - op2)); > + > + emit_insn (gen_floatsi<mode>2 (op2, operands[2])); > + emit_insn (gen_avx512f_scalef<mode>2 (operands[0], operands[1], op2)); > } > else > { > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 3957c86c3df..9233dfc6150 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -92,7 +92,6 @@ (define_c_enum "unspec" [ > UNSPEC_RCP14 > UNSPEC_RSQRT14 > UNSPEC_FIXUPIMM > - UNSPEC_SCALEF > UNSPEC_VTERNLOG > UNSPEC_GETEXP > UNSPEC_GETMANT > -- > 2.18.1 > Please ignore this, have replied in another thread.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 56b09c566ed..4a8e8fea290 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -125,6 +125,9 @@ (define_c_enum "unspec" [ UNSPEC_RSQRT UNSPEC_PSADBW + ;; For AVX512F support + UNSPEC_SCALEF + ;; Generic math support UNSPEC_COPYSIGN UNSPEC_XORSIGN @@ -17894,6 +17897,17 @@ (define_expand "expm1<mode>2" DONE; }) +(define_insn "avx512f_scalef<mode>2" + [(set (match_operand:MODEF 0 "register_operand" "=v") + (unspec:MODEF + [(match_operand:MODEF 1 "register_operand" "v") + (match_operand:MODEF 2 "nonimmediate_operand" "vm")] + UNSPEC_SCALEF))] + "TARGET_AVX512F" + "vscalef<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "<MODE>")]) + (define_expand "ldexpxf3" [(match_operand:XF 0 "register_operand") (match_operand:XF 1 "register_operand") @@ -17924,15 +17938,12 @@ (define_expand "ldexp<mode>3" if (TARGET_AVX512F && TARGET_SSE_MATH) { rtx op2 = gen_reg_rtx (<MODE>mode); - emit_insn (gen_floatsi<mode>2 (op2, operands[2])); - operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode); - if (MEM_P (operands[1])) + + if (!nonimmediate_operand (operands[1], <MODE>mode)) operands[1] = force_reg (<MODE>mode, operands[1]); - operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode); - op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode); - emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0], - operands[1], - op2)); + + emit_insn (gen_floatsi<mode>2 (op2, operands[2])); + emit_insn (gen_avx512f_scalef<mode>2 (operands[0], operands[1], op2)); } else { diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3957c86c3df..9233dfc6150 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -92,7 +92,6 @@ (define_c_enum "unspec" [ UNSPEC_RCP14 UNSPEC_RSQRT14 UNSPEC_FIXUPIMM - UNSPEC_SCALEF UNSPEC_VTERNLOG UNSPEC_GETEXP UNSPEC_GETMANT
Hi: This is the patch i'm going to checkin. Bootstrapped and regtested on x86_64-linux-gnu{-m32,}; 2021-08-12 Uros Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/98309 * config/i386/i386.md (avx512f_scalef<mode>2): New define_insn. (ldexp<mode>3): Adjust for new define_insn. (UNSPEC_SCALEF): Move from sse.md. * config/i386/sse.md (UNSPEC_SCALEF): Move to i386.md. --- gcc/config/i386/i386.md | 27 +++++++++++++++++++-------- gcc/config/i386/sse.md | 1 - 2 files changed, 19 insertions(+), 9 deletions(-)