diff mbox series

[06/10,RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns

Message ID 1660860233-11175-7-git-send-email-apinski@marvell.com
State New
Headers show
Series Fix/improve the RISCV backend | expand

Commit Message

Li, Pan2 via Gcc-patches Aug. 18, 2022, 10:03 p.m. UTC 
From: Andrew Pinski <apinski@marvell.com>

This simplifies the code by adding a predicate and a constraint for 1/2/3.
The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
which they use there.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.

Thanks,
Andrew Pinski

gcc/ChangeLog:

	* config/riscv/constraints.md (Ds3): New constraint.
	* config/riscv/predicates.md (imm123_operand): New predicate.
	* config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
	(*shNadduw): Likewise.
---
 gcc/config/riscv/bitmanip.md    | 8 +++-----
 gcc/config/riscv/constraints.md | 6 ++++++
 gcc/config/riscv/predicates.md  | 5 +++++
 3 files changed, 14 insertions(+), 5 deletions(-)

Comments

Kito Cheng Aug. 22, 2022, 8:47 a.m. UTC | #1 
I know using more precise constraints might result in better code gen
in some situations, but I am Curious what's the difference between the
using pattern condition and constraints/predicates in this case? Is
there any performance or code gen difference?

On Fri, Aug 19, 2022 at 6:07 AM apinski--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Andrew Pinski <apinski@marvell.com>
>
> This simplifies the code by adding a predicate and a constraint for 1/2/3.
> The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
> which they use there.
>
> OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.
>
> Thanks,
> Andrew Pinski
>
> gcc/ChangeLog:
>
>         * config/riscv/constraints.md (Ds3): New constraint.
>         * config/riscv/predicates.md (imm123_operand): New predicate.
>         * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
>         (*shNadduw): Likewise.
> ---
>  gcc/config/riscv/bitmanip.md    | 8 +++-----
>  gcc/config/riscv/constraints.md | 6 ++++++
>  gcc/config/riscv/predicates.md  | 5 +++++
>  3 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index ebd6eee1a22..73a36f7751b 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip"
>  (define_insn "*shNadd"
>    [(set (match_operand:X 0 "register_operand" "=r")
>         (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> -                         (match_operand:QI 2 "immediate_operand" "I"))
> +                         (match_operand:QI 2 "imm123_operand" "Ds3"))
>                 (match_operand:X 3 "register_operand" "r")))]
> -  "TARGET_ZBA
> -   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
> +  "TARGET_ZBA"
>    "sh%2add\t%0,%1,%3"
>    [(set_attr "type" "bitmanip")
>     (set_attr "mode" "<X:MODE>")])
> @@ -44,11 +43,10 @@ (define_insn "*shNadduw"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>         (plus:DI
>           (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> -                            (match_operand:QI 2 "immediate_operand" "I"))
> +                            (match_operand:QI 2 "imm123_operand" "Ds3"))
>                  (match_operand 3 "immediate_operand" ""))
>           (match_operand:DI 4 "register_operand" "r")))]
>    "TARGET_64BIT && TARGET_ZBA
> -   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
>     && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
>    "sh%2add.uw\t%0,%1,%4"
>    [(set_attr "type" "bitmanip")
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index bafa4188ccb..61b84875fd9 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -54,6 +54,12 @@ (define_constraint "L"
>    (and (match_code "const_int")
>         (match_test "LUI_OPERAND (ival)")))
>
> +(define_constraint "Ds3"
> +  "@internal
> +   1, 2 or 3 immediate"
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (ival, 1, 3)")))
> +
>  ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
>  ;; not available in RV32.
>  (define_constraint "G"
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 79e0c1d5589..2af7f661d6f 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -244,6 +244,11 @@ (define_predicate "imm5_operand"
>    (and (match_code "const_int")
>         (match_test "INTVAL (op) < 5")))
>
> +;; A const_int for sh1add/sh2add/sh3add
> +(define_predicate "imm123_operand"
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
> +
>  ;; A CONST_INT operand that consists of a single run of consecutive set bits.
>  (define_predicate "consecutive_bits_operand"
>    (match_code "const_int")
> --
> 2.27.0
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ebd6eee1a22..73a36f7751b 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -32,10 +32,9 @@  (define_insn "*zero_extendsidi2_bitmanip"
 (define_insn "*shNadd"
   [(set (match_operand:X 0 "register_operand" "=r")
 	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
-			  (match_operand:QI 2 "immediate_operand" "I"))
+			  (match_operand:QI 2 "imm123_operand" "Ds3"))
 		(match_operand:X 3 "register_operand" "r")))]
-  "TARGET_ZBA
-   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
+  "TARGET_ZBA"
   "sh%2add\t%0,%1,%3"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -44,11 +43,10 @@  (define_insn "*shNadduw"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI
 	  (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-			     (match_operand:QI 2 "immediate_operand" "I"))
+			     (match_operand:QI 2 "imm123_operand" "Ds3"))
 		 (match_operand 3 "immediate_operand" ""))
 	  (match_operand:DI 4 "register_operand" "r")))]
   "TARGET_64BIT && TARGET_ZBA
-   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
   "sh%2add.uw\t%0,%1,%4"
   [(set_attr "type" "bitmanip")
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb..61b84875fd9 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -54,6 +54,12 @@  (define_constraint "L"
   (and (match_code "const_int")
        (match_test "LUI_OPERAND (ival)")))
 
+(define_constraint "Ds3"
+  "@internal
+   1, 2 or 3 immediate"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 1, 3)")))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 79e0c1d5589..2af7f661d6f 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -244,6 +244,11 @@  (define_predicate "imm5_operand"
   (and (match_code "const_int")
        (match_test "INTVAL (op) < 5")))
 
+;; A const_int for sh1add/sh2add/sh3add
+(define_predicate "imm123_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
+
 ;; A CONST_INT operand that consists of a single run of consecutive set bits.
 (define_predicate "consecutive_bits_operand"
   (match_code "const_int")