| Message ID | 1597069297-42943-1-git-send-email-joe.ramsay@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55 | expand |
On 10/08/2020 15:21, Joe Ramsay wrote: > From: Joe Ramsay <Joe.Ramsay@arm.com> > > Hi, > > This patch rearranges feature bits for MVE and FP to implement the > following flags for -mcpu=cortex-m55. > > - +nomve: equivalent to armv8.1-m.main+fp.dp+dsp. > - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). > - +nofp: equivalent to armv8.1-m.main+mve (+dsp is implied by +mve). > - +nodsp: equivalent to armv8.1-m.main+fp.dp. > > Combinations of the above: > > - +nomve+nofp: equivalent to armv8.1-m.main+dsp. > - +nodsp+nofp: equivalent to armv8.1-m.main. > > Due to MVE and FP sharing vfp_base, some new syntax was required in the CPU > description to implement the concept of 'implied bits'. These are non-named > features added to the ISA late, depending on whether one or more features which > depend on them are present. This means vfp_base can be present when only one of > MVE and FP is removed, but absent when both are removed. > > Bootstrapped and tested on arm-none-eabi. OK for master? This all looks OK. But we need some additional tests in the multilib selection tests (testsuite/gcc.target/arm/multilib.exp) to make sure that the correct libraries are being picked when the new functionality is being required. R. > > Thanks all! > Joe > > gcc/ChangeLog: > > 2020-07-31 Joe Ramsay <joe.ramsay@arm.com> > > * config/arm/arm-cpus.in: > (ALL_FPU_INTERNAL): Remove vfp_base. > (VFPv2): Remove vfp_base. > (MVE): Remove vfp_base. > (vfp_base): Redefine as implied bit dependent on MVE or FP > (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. > * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. > * config/arm/parsecpu.awk: > (gen_isa): Print implied bits and their dependencies to ISA header. > (gen_data): Add parsing for implied feature bits. > > gcc/testsuite/ChangeLog: > > 2020-07-31 Joe Ramsay <joe.ramsay@arm.com> > > * gcc.target/arm/cortex-m55-nodsp-flag.c: New test. > * gcc.target/arm/cortex-m55-nodsp-nofp-flag.c: New test. > * gcc.target/arm/cortex-m55-nofp-flag.c: New test. > * gcc.target/arm/cortex-m55-nofp-nomve-flag.c: New test. > * gcc.target/arm/cortex-m55-nomve-flag.c: New test. > * gcc.target/arm/cortex-m55-nomve.fp-flag.c: New test. > --- > gcc/config/arm/arm-cpus.in | 26 ++++++++--- > gcc/config/arm/arm.c | 14 ++++++ > gcc/config/arm/parsecpu.awk | 51 ++++++++++++++++++++++ > .../gcc.target/arm/cortex-m55-nodsp-flag-hard.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nodsp-flag-softfp.c | 15 +++++++ > .../arm/cortex-m55-nodsp-nofp-flag-softfp.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nofp-flag-hard.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nofp-flag-softfp.c | 15 +++++++ > .../arm/cortex-m55-nofp-nomve-flag-softfp.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nomve-flag-hard.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nomve-flag-softfp.c | 15 +++++++ > .../gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c | 15 +++++++ > .../arm/cortex-m55-nomve.fp-flag-softfp.c | 15 +++++++ > 13 files changed, 234 insertions(+), 7 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c > create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c > > diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in > index c98f8ed..5083028 100644 > --- a/gcc/config/arm/arm-cpus.in > +++ b/gcc/config/arm/arm-cpus.in > @@ -135,10 +135,6 @@ define feature armv8_1m_main > # Floating point and Neon extensions. > # VFPv1 is not supported in GCC. > > -# This feature bit is enabled for all VFP, MVE and > -# MVE with floating point extensions. > -define feature vfp_base > - > # Vector floating point v2. > define feature vfpv2 > > @@ -251,7 +247,7 @@ define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL > > # List of all FPU bits to strip out if -mfpu is used to override the > # default. fp16 is deliberately missing from this list. > -define fgroup ALL_FPU_INTERNAL vfp_base vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL > +define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL > # Similarly, but including fp16 and other extensions that aren't part of > # -mfpu support. > define fgroup ALL_FPU_EXTERNAL fp16 bf16 > @@ -296,11 +292,11 @@ define fgroup ARMv8r ARMv8a > define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main > > # Useful combinations. > -define fgroup VFPv2 vfp_base vfpv2 > +define fgroup VFPv2 vfpv2 > define fgroup VFPv3 VFPv2 vfpv3 > define fgroup VFPv4 VFPv3 vfpv4 fp16conv > define fgroup FPv5 VFPv4 fpv5 > -define fgroup MVE mve vfp_base armv7em > +define fgroup MVE mve armv7em > define fgroup MVE_FP MVE FPv5 fp16 mve_float > > define fgroup FP_DBL fp_dbl > @@ -310,6 +306,18 @@ define fgroup NEON FP_D32 neon > define fgroup CRYPTO NEON crypto > define fgroup DOTPROD NEON dotprod > > +# Implied feature bits. These are for non-named features shared between fgroups. > +# Shared feature f belonging to fgroups A and B will be erroneously removed if: > +# A and B are enabled by default AND A is disabled by a removal flag. > +# To ensure that f is retained, we must add such bits to the ISA after > +# processing the removal flags. This is implemented by 'implied bits': > +# define implied <name> [<feature-or-fgroup>]+ > +# This indicates that, if any of the listed features are enabled, or if any > +# member of a listed fgroup is enabled, then <name> will be implicitly enabled. > + > +# Enabled for all VFP, MVE and MVE with floating point extensions. > +define implied vfp_base MVE MVE_FP ALL_FP > + > # List of all quirk bits to strip out when comparing CPU features with > # architectures. > # xscale isn't really a 'quirk', but it isn't an architecture either and we > @@ -1508,6 +1516,10 @@ begin cpu cortex-m55 > cname cortexm55 > tune flags LDSCHED > architecture armv8.1-m.main+mve.fp+fp.dp > + option nomve.fp remove mve_float > + option nomve remove mve mve_float > + option nofp remove ALL_FP mve_float > + option nodsp remove MVE mve_float > isa quirk_no_asmcpu > costs v7m > vendor 41 > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index dd78141..dc03c7a 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -3410,6 +3410,20 @@ arm_configure_build_target (struct arm_build_target *target, > bitmap_ior (target->isa, target->isa, fpu_bits); > } > > + /* There may be implied bits which we still need to enable. These are > + non-named features which are needed to complete other sets of features, > + but cannot be enabled from arm-cpus.in due to being shared between > + multiple fgroups. Each entry in all_implied_fbits is of the form > + ante -> cons, meaning that if the feature "ante" is enabled, we should > + implicitly enable "cons". */ > + const struct fbit_implication *impl = all_implied_fbits; > + while (impl->ante) > + { > + if (bitmap_bit_p (target->isa, impl->ante)) > + bitmap_set_bit (target->isa, impl->cons); > + impl++; > + } > + > if (!arm_selected_tune) > arm_selected_tune = arm_selected_cpu; > else /* Validate the features passed to -mtune. */ > diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk > index 7fc3754..9423e8a 100644 > --- a/gcc/config/arm/parsecpu.awk > +++ b/gcc/config/arm/parsecpu.awk > @@ -190,6 +190,23 @@ function gen_isa () { > ORS = z > print "\n" > } > + > + print "struct fbit_implication {" > + print " /* Represents a feature implication, where:" > + print " ante IMPLIES cons" > + print " meaning that if ante is enabled then we should" > + print " also implicitly enable cons. */" > + print " enum isa_feature ante;" > + print " enum isa_feature cons;" > + print "};\n" > + print "static const struct fbit_implication all_implied_fbits[] =" > + print "{" > + for (impl in implied_bits) { > + split (impl, impl_parts, SUBSEP) > + print " { isa_bit_" impl_parts[2] ", isa_bit_" impl_parts[1] " }," > + } > + print " { isa_nobit, isa_nobit }" > + print "};\n" > } > > function gen_data () { > @@ -600,6 +617,40 @@ BEGIN { > parse_ok = 1 > } > > +/^define implied / { > + if (NF < 4) fatal("syntax: define implied <name> [<feature-or-fgroup>]+\n" \ > + "Implied bits must be defined with at least one antecedent.") > + toplevel() > + fbit = $3 > + if (fbit in features) fatal("implied feature " fbit " aliases a real feature") > + if (fbit in fgroup) fatal("implied feature " fbit " aliases a feature group") > + fcount = NF > + features[fbit] = 1 > + for (n = 4; n <= fcount; n++) { > + ante = $n > + if (fbit == ante) fatal("feature cannot imply itself") > + else if (ante in features) { > + for (impl in implied_bits) { > + split(impl, impl_sep, SUBSEP) > + if (ante == impl_sep[1]) > + fatal(ante " implies implied bit " fbit \ > + ". Chained implications not currently supported") > + } > + implied_bits[fbit, ante] = 1 > + } else if (ante in fgroup) { > + for (bitcomb in fgrp_bits) { > + split(bitcomb, bitsep, SUBSEP) > + if (bitsep[1] == ante) { > + implied_bits[fbit, bitsep[2]] = 1 > + } > + } > + } else { > + fatal("implied bit antecedent " ante " unrecognized") > + } > + } > + parse_ok = 1 > +} > + > /^begin fpu / { > if (NF != 3) fatal("syntax: begin fpu <name>") > toplevel() > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c > new file mode 100644 > index 0000000..b3c7fd0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=hard -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c > new file mode 100644 > index 0000000..3806554 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c > new file mode 100644 > index 0000000..d22eb4e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nodsp+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler "\.fpu softvfp" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c > new file mode 100644 > index 0000000..da1cc25 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=hard -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler-not "\.fpu" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c > new file mode 100644 > index 0000000..0a4fb14 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler-not "\.fpu" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c > new file mode 100644 > index 0000000..2ae7f34 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nomve+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler-not "\.fpu" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c > new file mode 100644 > index 0000000..a6ccd7b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=hard -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c > new file mode 100644 > index 0000000..2ad976a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c > new file mode 100644 > index 0000000..40d54b8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=hard -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > + > +int > +f () > +{ > + return 1; > +} > diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c > new file mode 100644 > index 0000000..c726803 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c > @@ -0,0 +1,15 @@ > +/* { dg-do assemble } */ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ > +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ > +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ > +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ > +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ > + > +int > +f () > +{ > + return 1; > +} >
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index c98f8ed..5083028 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -135,10 +135,6 @@ define feature armv8_1m_main # Floating point and Neon extensions. # VFPv1 is not supported in GCC. -# This feature bit is enabled for all VFP, MVE and -# MVE with floating point extensions. -define feature vfp_base - # Vector floating point v2. define feature vfpv2 @@ -251,7 +247,7 @@ define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL # List of all FPU bits to strip out if -mfpu is used to override the # default. fp16 is deliberately missing from this list. -define fgroup ALL_FPU_INTERNAL vfp_base vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL +define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL # Similarly, but including fp16 and other extensions that aren't part of # -mfpu support. define fgroup ALL_FPU_EXTERNAL fp16 bf16 @@ -296,11 +292,11 @@ define fgroup ARMv8r ARMv8a define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main # Useful combinations. -define fgroup VFPv2 vfp_base vfpv2 +define fgroup VFPv2 vfpv2 define fgroup VFPv3 VFPv2 vfpv3 define fgroup VFPv4 VFPv3 vfpv4 fp16conv define fgroup FPv5 VFPv4 fpv5 -define fgroup MVE mve vfp_base armv7em +define fgroup MVE mve armv7em define fgroup MVE_FP MVE FPv5 fp16 mve_float define fgroup FP_DBL fp_dbl @@ -310,6 +306,18 @@ define fgroup NEON FP_D32 neon define fgroup CRYPTO NEON crypto define fgroup DOTPROD NEON dotprod +# Implied feature bits. These are for non-named features shared between fgroups. +# Shared feature f belonging to fgroups A and B will be erroneously removed if: +# A and B are enabled by default AND A is disabled by a removal flag. +# To ensure that f is retained, we must add such bits to the ISA after +# processing the removal flags. This is implemented by 'implied bits': +# define implied <name> [<feature-or-fgroup>]+ +# This indicates that, if any of the listed features are enabled, or if any +# member of a listed fgroup is enabled, then <name> will be implicitly enabled. + +# Enabled for all VFP, MVE and MVE with floating point extensions. +define implied vfp_base MVE MVE_FP ALL_FP + # List of all quirk bits to strip out when comparing CPU features with # architectures. # xscale isn't really a 'quirk', but it isn't an architecture either and we @@ -1508,6 +1516,10 @@ begin cpu cortex-m55 cname cortexm55 tune flags LDSCHED architecture armv8.1-m.main+mve.fp+fp.dp + option nomve.fp remove mve_float + option nomve remove mve mve_float + option nofp remove ALL_FP mve_float + option nodsp remove MVE mve_float isa quirk_no_asmcpu costs v7m vendor 41 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dd78141..dc03c7a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3410,6 +3410,20 @@ arm_configure_build_target (struct arm_build_target *target, bitmap_ior (target->isa, target->isa, fpu_bits); } + /* There may be implied bits which we still need to enable. These are + non-named features which are needed to complete other sets of features, + but cannot be enabled from arm-cpus.in due to being shared between + multiple fgroups. Each entry in all_implied_fbits is of the form + ante -> cons, meaning that if the feature "ante" is enabled, we should + implicitly enable "cons". */ + const struct fbit_implication *impl = all_implied_fbits; + while (impl->ante) + { + if (bitmap_bit_p (target->isa, impl->ante)) + bitmap_set_bit (target->isa, impl->cons); + impl++; + } + if (!arm_selected_tune) arm_selected_tune = arm_selected_cpu; else /* Validate the features passed to -mtune. */ diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 7fc3754..9423e8a 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -190,6 +190,23 @@ function gen_isa () { ORS = z print "\n" } + + print "struct fbit_implication {" + print " /* Represents a feature implication, where:" + print " ante IMPLIES cons" + print " meaning that if ante is enabled then we should" + print " also implicitly enable cons. */" + print " enum isa_feature ante;" + print " enum isa_feature cons;" + print "};\n" + print "static const struct fbit_implication all_implied_fbits[] =" + print "{" + for (impl in implied_bits) { + split (impl, impl_parts, SUBSEP) + print " { isa_bit_" impl_parts[2] ", isa_bit_" impl_parts[1] " }," + } + print " { isa_nobit, isa_nobit }" + print "};\n" } function gen_data () { @@ -600,6 +617,40 @@ BEGIN { parse_ok = 1 } +/^define implied / { + if (NF < 4) fatal("syntax: define implied <name> [<feature-or-fgroup>]+\n" \ + "Implied bits must be defined with at least one antecedent.") + toplevel() + fbit = $3 + if (fbit in features) fatal("implied feature " fbit " aliases a real feature") + if (fbit in fgroup) fatal("implied feature " fbit " aliases a feature group") + fcount = NF + features[fbit] = 1 + for (n = 4; n <= fcount; n++) { + ante = $n + if (fbit == ante) fatal("feature cannot imply itself") + else if (ante in features) { + for (impl in implied_bits) { + split(impl, impl_sep, SUBSEP) + if (ante == impl_sep[1]) + fatal(ante " implies implied bit " fbit \ + ". Chained implications not currently supported") + } + implied_bits[fbit, ante] = 1 + } else if (ante in fgroup) { + for (bitcomb in fgrp_bits) { + split(bitcomb, bitsep, SUBSEP) + if (bitsep[1] == ante) { + implied_bits[fbit, bitsep[2]] = 1 + } + } + } else { + fatal("implied bit antecedent " ante " unrecognized") + } + } + parse_ok = 1 +} + /^begin fpu / { if (NF != 3) fatal("syntax: begin fpu <name>") toplevel() diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c new file mode 100644 index 0000000..b3c7fd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c new file mode 100644 index 0000000..3806554 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c new file mode 100644 index 0000000..d22eb4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu softvfp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c new file mode 100644 index 0000000..da1cc25 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c new file mode 100644 index 0000000..0a4fb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c new file mode 100644 index 0000000..2ae7f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c new file mode 100644 index 0000000..a6ccd7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c new file mode 100644 index 0000000..2ad976a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c new file mode 100644 index 0000000..40d54b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c new file mode 100644 index 0000000..c726803 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +}
From: Joe Ramsay <Joe.Ramsay@arm.com> Hi, This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve: equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to armv8.1-m.main+mve (+dsp is implied by +mve). - +nodsp: equivalent to armv8.1-m.main+fp.dp. Combinations of the above: - +nomve+nofp: equivalent to armv8.1-m.main+dsp. - +nodsp+nofp: equivalent to armv8.1-m.main. Due to MVE and FP sharing vfp_base, some new syntax was required in the CPU description to implement the concept of 'implied bits'. These are non-named features added to the ISA late, depending on whether one or more features which depend on them are present. This means vfp_base can be present when only one of MVE and FP is removed, but absent when both are removed. Bootstrapped and tested on arm-none-eabi. OK for master? Thanks all! Joe gcc/ChangeLog: 2020-07-31 Joe Ramsay <joe.ramsay@arm.com> * config/arm/arm-cpus.in: (ALL_FPU_INTERNAL): Remove vfp_base. (VFPv2): Remove vfp_base. (MVE): Remove vfp_base. (vfp_base): Redefine as implied bit dependent on MVE or FP (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. * config/arm/parsecpu.awk: (gen_isa): Print implied bits and their dependencies to ISA header. (gen_data): Add parsing for implied feature bits. gcc/testsuite/ChangeLog: 2020-07-31 Joe Ramsay <joe.ramsay@arm.com> * gcc.target/arm/cortex-m55-nodsp-flag.c: New test. * gcc.target/arm/cortex-m55-nodsp-nofp-flag.c: New test. * gcc.target/arm/cortex-m55-nofp-flag.c: New test. * gcc.target/arm/cortex-m55-nofp-nomve-flag.c: New test. * gcc.target/arm/cortex-m55-nomve-flag.c: New test. * gcc.target/arm/cortex-m55-nomve.fp-flag.c: New test. --- gcc/config/arm/arm-cpus.in | 26 ++++++++--- gcc/config/arm/arm.c | 14 ++++++ gcc/config/arm/parsecpu.awk | 51 ++++++++++++++++++++++ .../gcc.target/arm/cortex-m55-nodsp-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nodsp-flag-softfp.c | 15 +++++++ .../arm/cortex-m55-nodsp-nofp-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nofp-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nofp-flag-softfp.c | 15 +++++++ .../arm/cortex-m55-nofp-nomve-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c | 15 +++++++ .../arm/cortex-m55-nomve.fp-flag-softfp.c | 15 +++++++ 13 files changed, 234 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c