From patchwork Mon Aug 10 14:21:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joe Ramsay X-Patchwork-Id: 1342846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BQJ7P5TYKz9sT6 for ; Tue, 11 Aug 2020 00:21:52 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0789C385703B; Mon, 10 Aug 2020 14:21:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id C2329385702F for ; Mon, 10 Aug 2020 14:21:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C2329385702F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=joe.ramsay@arm.com Received: from fw-tnat-cam4.arm.com ([217.140.106.52]:59445 helo=cam-smtp0.cambridge.arm.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k58gI-0007Gh-1G for gcc-patches@gcc.gnu.org; Mon, 10 Aug 2020 10:21:45 -0400 Received: from man-06.manchester.arm.com (man-06.manchester.arm.com [10.32.108.34]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id 07AELbXD026009; Mon, 10 Aug 2020 15:21:37 +0100 From: Joe Ramsay To: joe.ramsay@arm.com, gcc-patches@gcc.gnu.org Subject: [PATCH] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55 Date: Mon, 10 Aug 2020 14:21:37 +0000 Message-Id: <1597069297-42943-1-git-send-email-joe.ramsay@arm.com> X-Mailer: git-send-email 2.7.4 Received-SPF: pass client-ip=217.140.106.52; envelope-from=joe.ramsay@arm.com; helo=cam-smtp0.cambridge.arm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/10 10:21:38 X-ACL-Warn: Detected OS = Linux 2.6.x [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-17.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, SPF_FAIL, SPF_HELO_NONE, TO_EQ_FM_DOM_SPF_FAIL, TO_EQ_FM_SPF_FAIL, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" From: Joe Ramsay Hi, This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve: equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to armv8.1-m.main+mve (+dsp is implied by +mve). - +nodsp: equivalent to armv8.1-m.main+fp.dp. Combinations of the above: - +nomve+nofp: equivalent to armv8.1-m.main+dsp. - +nodsp+nofp: equivalent to armv8.1-m.main. Due to MVE and FP sharing vfp_base, some new syntax was required in the CPU description to implement the concept of 'implied bits'. These are non-named features added to the ISA late, depending on whether one or more features which depend on them are present. This means vfp_base can be present when only one of MVE and FP is removed, but absent when both are removed. Bootstrapped and tested on arm-none-eabi. OK for master? Thanks all! Joe gcc/ChangeLog: 2020-07-31 Joe Ramsay * config/arm/arm-cpus.in: (ALL_FPU_INTERNAL): Remove vfp_base. (VFPv2): Remove vfp_base. (MVE): Remove vfp_base. (vfp_base): Redefine as implied bit dependent on MVE or FP (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. * config/arm/parsecpu.awk: (gen_isa): Print implied bits and their dependencies to ISA header. (gen_data): Add parsing for implied feature bits. gcc/testsuite/ChangeLog: 2020-07-31 Joe Ramsay * gcc.target/arm/cortex-m55-nodsp-flag.c: New test. * gcc.target/arm/cortex-m55-nodsp-nofp-flag.c: New test. * gcc.target/arm/cortex-m55-nofp-flag.c: New test. * gcc.target/arm/cortex-m55-nofp-nomve-flag.c: New test. * gcc.target/arm/cortex-m55-nomve-flag.c: New test. * gcc.target/arm/cortex-m55-nomve.fp-flag.c: New test. --- gcc/config/arm/arm-cpus.in | 26 ++++++++--- gcc/config/arm/arm.c | 14 ++++++ gcc/config/arm/parsecpu.awk | 51 ++++++++++++++++++++++ .../gcc.target/arm/cortex-m55-nodsp-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nodsp-flag-softfp.c | 15 +++++++ .../arm/cortex-m55-nodsp-nofp-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nofp-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nofp-flag-softfp.c | 15 +++++++ .../arm/cortex-m55-nofp-nomve-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve-flag-hard.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve-flag-softfp.c | 15 +++++++ .../gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c | 15 +++++++ .../arm/cortex-m55-nomve.fp-flag-softfp.c | 15 +++++++ 13 files changed, 234 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c create mode 100644 gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index c98f8ed..5083028 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -135,10 +135,6 @@ define feature armv8_1m_main # Floating point and Neon extensions. # VFPv1 is not supported in GCC. -# This feature bit is enabled for all VFP, MVE and -# MVE with floating point extensions. -define feature vfp_base - # Vector floating point v2. define feature vfpv2 @@ -251,7 +247,7 @@ define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL # List of all FPU bits to strip out if -mfpu is used to override the # default. fp16 is deliberately missing from this list. -define fgroup ALL_FPU_INTERNAL vfp_base vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL +define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL # Similarly, but including fp16 and other extensions that aren't part of # -mfpu support. define fgroup ALL_FPU_EXTERNAL fp16 bf16 @@ -296,11 +292,11 @@ define fgroup ARMv8r ARMv8a define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main # Useful combinations. -define fgroup VFPv2 vfp_base vfpv2 +define fgroup VFPv2 vfpv2 define fgroup VFPv3 VFPv2 vfpv3 define fgroup VFPv4 VFPv3 vfpv4 fp16conv define fgroup FPv5 VFPv4 fpv5 -define fgroup MVE mve vfp_base armv7em +define fgroup MVE mve armv7em define fgroup MVE_FP MVE FPv5 fp16 mve_float define fgroup FP_DBL fp_dbl @@ -310,6 +306,18 @@ define fgroup NEON FP_D32 neon define fgroup CRYPTO NEON crypto define fgroup DOTPROD NEON dotprod +# Implied feature bits. These are for non-named features shared between fgroups. +# Shared feature f belonging to fgroups A and B will be erroneously removed if: +# A and B are enabled by default AND A is disabled by a removal flag. +# To ensure that f is retained, we must add such bits to the ISA after +# processing the removal flags. This is implemented by 'implied bits': +# define implied []+ +# This indicates that, if any of the listed features are enabled, or if any +# member of a listed fgroup is enabled, then will be implicitly enabled. + +# Enabled for all VFP, MVE and MVE with floating point extensions. +define implied vfp_base MVE MVE_FP ALL_FP + # List of all quirk bits to strip out when comparing CPU features with # architectures. # xscale isn't really a 'quirk', but it isn't an architecture either and we @@ -1508,6 +1516,10 @@ begin cpu cortex-m55 cname cortexm55 tune flags LDSCHED architecture armv8.1-m.main+mve.fp+fp.dp + option nomve.fp remove mve_float + option nomve remove mve mve_float + option nofp remove ALL_FP mve_float + option nodsp remove MVE mve_float isa quirk_no_asmcpu costs v7m vendor 41 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dd78141..dc03c7a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3410,6 +3410,20 @@ arm_configure_build_target (struct arm_build_target *target, bitmap_ior (target->isa, target->isa, fpu_bits); } + /* There may be implied bits which we still need to enable. These are + non-named features which are needed to complete other sets of features, + but cannot be enabled from arm-cpus.in due to being shared between + multiple fgroups. Each entry in all_implied_fbits is of the form + ante -> cons, meaning that if the feature "ante" is enabled, we should + implicitly enable "cons". */ + const struct fbit_implication *impl = all_implied_fbits; + while (impl->ante) + { + if (bitmap_bit_p (target->isa, impl->ante)) + bitmap_set_bit (target->isa, impl->cons); + impl++; + } + if (!arm_selected_tune) arm_selected_tune = arm_selected_cpu; else /* Validate the features passed to -mtune. */ diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 7fc3754..9423e8a 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -190,6 +190,23 @@ function gen_isa () { ORS = z print "\n" } + + print "struct fbit_implication {" + print " /* Represents a feature implication, where:" + print " ante IMPLIES cons" + print " meaning that if ante is enabled then we should" + print " also implicitly enable cons. */" + print " enum isa_feature ante;" + print " enum isa_feature cons;" + print "};\n" + print "static const struct fbit_implication all_implied_fbits[] =" + print "{" + for (impl in implied_bits) { + split (impl, impl_parts, SUBSEP) + print " { isa_bit_" impl_parts[2] ", isa_bit_" impl_parts[1] " }," + } + print " { isa_nobit, isa_nobit }" + print "};\n" } function gen_data () { @@ -600,6 +617,40 @@ BEGIN { parse_ok = 1 } +/^define implied / { + if (NF < 4) fatal("syntax: define implied []+\n" \ + "Implied bits must be defined with at least one antecedent.") + toplevel() + fbit = $3 + if (fbit in features) fatal("implied feature " fbit " aliases a real feature") + if (fbit in fgroup) fatal("implied feature " fbit " aliases a feature group") + fcount = NF + features[fbit] = 1 + for (n = 4; n <= fcount; n++) { + ante = $n + if (fbit == ante) fatal("feature cannot imply itself") + else if (ante in features) { + for (impl in implied_bits) { + split(impl, impl_sep, SUBSEP) + if (ante == impl_sep[1]) + fatal(ante " implies implied bit " fbit \ + ". Chained implications not currently supported") + } + implied_bits[fbit, ante] = 1 + } else if (ante in fgroup) { + for (bitcomb in fgrp_bits) { + split(bitcomb, bitsep, SUBSEP) + if (bitsep[1] == ante) { + implied_bits[fbit, bitsep[2]] = 1 + } + } + } else { + fatal("implied bit antecedent " ante " unrecognized") + } + } + parse_ok = 1 +} + /^begin fpu / { if (NF != 3) fatal("syntax: begin fpu ") toplevel() diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c new file mode 100644 index 0000000..b3c7fd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c new file mode 100644 index 0000000..3806554 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c new file mode 100644 index 0000000..d22eb4e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nodsp+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.fpu softvfp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c new file mode 100644 index 0000000..da1cc25 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c new file mode 100644 index 0000000..0a4fb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c new file mode 100644 index 0000000..2ae7f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve+nofp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler-not "\.fpu" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c new file mode 100644 index 0000000..a6ccd7b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c new file mode 100644 index 0000000..2ad976a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c new file mode 100644 index 0000000..40d54b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=hard -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +} diff --git a/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c new file mode 100644 index 0000000..c726803 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-additional-options "-mcpu=cortex-m55+nomve.fp -mfloat-abi=softfp -mfpu=auto --save-temps" } */ +/* { dg-final { scan-assembler-not "\.arch_extension mve.fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension mve" } } */ +/* { dg-final { scan-assembler "\.arch_extension dsp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp" } } */ +/* { dg-final { scan-assembler "\.arch_extension fp.dp" } } */ +/* { dg-final { scan-assembler "\.fpu fpv5-d16" } } */ + +int +f () +{ + return 1; +}