diff mbox series

nvptx: Support 16-bit shifts and extendqihi2.

Message ID 007701d657b3$539c6810$fad53830$@nextmovesoftware.com
State New
Headers show
Series nvptx: Support 16-bit shifts and extendqihi2. | expand

Commit Message

Roger Sayle July 11, 2020, 6:44 p.m. UTC 
The following patch adds support for 16-bits shifts and for sign extension
from 8 bits to 16 bits.

This patch has been tested on nvptx-none with no new regressions.
Ok for mainline?

2020-07-11  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
        * config/nvptx/nvptx.md (extendqihi2): New instruction.
        (ashl<mode>3, ashr<mode>3, lshr<mode>3): Support HImode.


Thanks in advance,
Roger
--
Roger Sayle
NextMove Software
Cambridge, UK

Comments

Tom de Vries July 28, 2020, 1:15 p.m. UTC | #1 
On 7/11/20 8:44 PM, Roger Sayle wrote:
> The following patch adds support for 16-bits shifts and for sign extension
> from 8 bits to 16 bits.
> 
> This patch has been tested on nvptx-none with no new regressions.
> Ok for mainline?
> 
> 2020-07-11  Roger Sayle  <roger@nextmovesoftware.com>
> 
> gcc/ChangeLog
>         * config/nvptx/nvptx.md (extendqihi2): New instruction.
>         (ashl<mode>3, ashr<mode>3, lshr<mode>3): Support HImode.
> 
> 

Pushed as attached, with test-case added.

Thanks,
- Tom
diff mbox series

Patch

diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index 6545b81..0538e83 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -319,6 +319,13 @@ 
    %.\\tld%A1%u1\\t%0, %1;"
   [(set_attr "subregs_ok" "true")])
 
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "nvptx_register_operand" "=R")
+	(sign_extend:HI (match_operand:QI 1 "nvptx_register_operand" "R")))]
+  ""
+  "%.\\tcvt.s16.s8\\t%0, %1;"
+  [(set_attr "subregs_ok" "true")])
+
 (define_insn "extend<mode>si2"
   [(set (match_operand:SI 0 "nvptx_register_operand" "=R,R")
 	(sign_extend:SI (match_operand:QHIM 1 "nvptx_nonimmediate_operand" "R,m")))]
@@ -556,23 +563,23 @@ 
 ;; Shifts
 
 (define_insn "ashl<mode>3"
-  [(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
-	(ashift:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
-		     (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
+  [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
+	(ashift:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
+		      (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
   ""
   "%.\\tshl.b%T0\\t%0, %1, %2;")
 
 (define_insn "ashr<mode>3"
-  [(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
-	(ashiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
-		       (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
+  [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
+	(ashiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
+			(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
   ""
   "%.\\tshr.s%T0\\t%0, %1, %2;")
 
 (define_insn "lshr<mode>3"
-  [(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
-	(lshiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
-		       (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
+  [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
+	(lshiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
+			(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
   ""
   "%.\\tshr.u%T0\\t%0, %1, %2;")