Show patches with: Submitter = Vineet Gupta       |    State = Action Required       |    Archived = No       |   137 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[COMMITTED] RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] [COMMITTED] RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] - 1 - - --- 2025-08-15 Vineet Gupta New
[v2] RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] [v2] RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] - 1 - - --- 2025-08-15 Vineet Gupta New
RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] RISC-V: fix __builtin_round clobbering FP exceptions flags [PR121534] 1 1 - - --- 2025-08-14 Vineet Gupta New
[COMMITTED,2/2] RISC-V: prefetch: fix LRA failing to allocate reg [PR118241] [COMMITTED,1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 - - - - --- 2025-07-04 Vineet Gupta New
[COMMITTED,1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 [COMMITTED,1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 - - - - --- 2025-07-04 Vineet Gupta New
[2/2] RISC-V: prefetch: fix LRA ICE [PR118241] [1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 - - - - --- 2025-07-03 Vineet Gupta New
[1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 [1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 - - - - --- 2025-07-03 Vineet Gupta New
[COMMITTED] RISC-V: testsuite: fix an obvious build error [COMMITTED] RISC-V: testsuite: fix an obvious build error - - - - --- 2025-06-10 Vineet Gupta New
RISC-V: testsuite: fix an obvious build error RISC-V: testsuite: fix an obvious build error - - - - --- 2025-06-10 Vineet Gupta New
[COMMITTED,5/5] RISC-V: frm/mode-switch: robustify call_insn backtracking [PR120203] [COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB - - - - --- 2025-06-08 Vineet Gupta New
[COMMITTED,4/5] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164] [COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB - - - - --- 2025-06-08 Vineet Gupta New
[COMMITTED,3/5] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn [COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB - - - - --- 2025-06-08 Vineet Gupta New
[COMMITTED,2/5] RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE [COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB - - - - --- 2025-06-08 Vineet Gupta New
[COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB [COMMITTED,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB - - - - --- 2025-06-08 Vineet Gupta New
[v2,5/5] RISC-V: frm/mode-switch: robustify call_insn backtracking [PR120203] RISC-V: frm state-machine improvements - - - - --- 2025-06-06 Vineet Gupta New
[v2,4/5] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164] RISC-V: frm state-machine improvements - - - - --- 2025-06-06 Vineet Gupta New
[v2,3/5] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn RISC-V: frm state-machine improvements - - - - --- 2025-06-06 Vineet Gupta New
[v2,2/5] RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE RISC-V: frm state-machine improvements - - - - --- 2025-06-06 Vineet Gupta New
[v2,1/5] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB RISC-V: frm state-machine improvements - - - - --- 2025-06-06 Vineet Gupta New
[6/6] RISC-V: frm/mode-switch: robustify call_insn backtracking [PR119164][PR120203] RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[5/6] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[4/6] RISC-V: frm/mode-switch: TARGET_MODE_AFTER not needed for frm switching RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[3/6] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[2/6] RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[1/6] emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into next BB RISC-V: frm state-machine improvements - - - - --- 2025-05-09 Vineet Gupta New
[COMMITTED] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] [COMMITTED] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] - - - - --- 2025-04-15 Vineet Gupta New
[v2] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] [v2] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] - - - - --- 2025-04-09 Vineet Gupta New
[v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533] [v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533] - - - - --- 2025-03-30 Vineet Gupta New
RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533] - - - - --- 2025-03-29 Vineet Gupta New
[COMMITTED] RISC-V: disable the abd expander for gcc-15 release [PR119224] [COMMITTED] RISC-V: disable the abd expander for gcc-15 release [PR119224] - - - - --- 2025-03-25 Vineet Gupta New
RISC-V: disable the abd expander for gcc-15 release [PR119224] RISC-V: disable the abd expander for gcc-15 release [PR119224] - - - - --- 2025-03-24 Vineet Gupta New
[COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 [COMMITTED] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 - - - - --- 2025-02-12 Vineet Gupta New
[v2] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 [v2] RISC-V: Vector pesudoinsns with x0 operand to use imm 0 - - - - --- 2025-02-08 Vineet Gupta New
RISC-V: Vector pesudoinsns with x0 operand to use imm 0. (toggle) RISC-V: Vector pesudoinsns with x0 operand to use imm 0. (toggle) - - - - --- 2025-02-07 Vineet Gupta New
[COMMITTED] RISC-V: Add another test for FRM elimination bug [PR118646] [COMMITTED] RISC-V: Add another test for FRM elimination bug [PR118646] - - - - --- 2025-01-27 Vineet Gupta New
RISC-V: ensure needed FRM restore is not eliminable [PR118646] RISC-V: ensure needed FRM restore is not eliminable [PR118646] - - - - --- 2025-01-24 Vineet Gupta New
[COMMITTED] RISC-V: fix thinko in riscv_register_move_cost () [COMMITTED] RISC-V: fix thinko in riscv_register_move_cost () - 1 - - --- 2025-01-13 Vineet Gupta New
RISC-V: fix thinko in riscv_register_move_cost () RISC-V: fix thinko in riscv_register_move_cost () - 1 - - --- 2025-01-11 Vineet Gupta New
[COMMITTED] RISC-V: vector absolute difference expander [PR117722] [COMMITTED] RISC-V: vector absolute difference expander [PR117722] - - - - --- 2025-01-07 Vineet Gupta New
[v2] RISC-V: vector absolute difference expander [PR117722] [v2] RISC-V: vector absolute difference expander [PR117722] - - - - --- 2024-12-20 Vineet Gupta New
RISC-V: vector absolute difference expander [PR117722] RISC-V: vector absolute difference expander [PR117722] - - - - --- 2024-12-20 Vineet Gupta New
[COMMITTED,2/2] sched1: debug/model: dump predecessor list and BB num [NFC] [COMMITTED,1/2] sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729] - - - - --- 2024-12-04 Vineet Gupta New
[COMMITTED,1/2] sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729] [COMMITTED,1/2] sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729] - - - - --- 2024-12-04 Vineet Gupta New
sched1: debug/model: dump predecessor list and BB num [NFC] sched1: debug/model: dump predecessor list and BB num [NFC] - - - - --- 2024-11-05 Vineet Gupta New
[v2] sched1: parameterize pressure scheduling spilling agressiveness [PR/114729] [v2] sched1: parameterize pressure scheduling spilling agressiveness [PR/114729] - - - - --- 2024-11-05 Vineet Gupta New
[COMMITTED] RISC-V: fix const interleaved stepped vector with a scalar pattern [COMMITTED] RISC-V: fix const interleaved stepped vector with a scalar pattern - - - 1 --- 2024-10-31 Vineet Gupta New
RISC-V: fix const interleaved stepped vector with a scalar pattern RISC-V: fix const interleaved stepped vector with a scalar pattern - - - - --- 2024-10-30 Vineet Gupta New
[4/4] sched1: model: ICE on infinite loops in predecessor promotion (Not for Merge) sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[3/4] sched1: model: only promote true dependecies in predecessor promotion sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[2/4] RISC-V: Implement TARGET_SCHED_PRESSURE_PREFER_NARROW [PR/114729] sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[1/4] sched1: hookize pressure scheduling spilling agressiveness sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
RFC model schedule tweak (was Re: sched1 pathology on RISC-V : PR/114729) RFC model schedule tweak (was Re: sched1 pathology on RISC-V : PR/114729) - - - - --- 2024-09-10 Vineet Gupta New
[COMMITTED] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [COMMITTED] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - 1 --- 2024-08-15 Vineet Gupta New
[RESEND,v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [RESEND,v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-08-15 Vineet Gupta New
[COMMITTED] RISC-V: Fix snafu in SI mode splitters patch [COMMITTED] RISC-V: Fix snafu in SI mode splitters patch - - - - --- 2024-07-23 Vineet Gupta New
[v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-13 Vineet Gupta New
[v4] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v4] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-13 Vineet Gupta New
[v3] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v3] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-12 Vineet Gupta New
[v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins [v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins - - - - --- 2024-07-01 Vineet Gupta New
RISC-V: use fclass insns to implement isfinite and isnormal builtins RISC-V: use fclass insns to implement isfinite and isnormal builtins - - - - --- 2024-06-29 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const mat in alloca epilogue expansion [COMMITTED] RISC-V: avoid LUI based const mat in alloca epilogue expansion - - - 1 --- 2024-05-21 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] [COMMITTED] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - 1 --- 2024-05-21 Vineet Gupta New
[v3,2/2] RISC-V: avoid LUI based const mat in alloca epilogue expansion [v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - - --- 2024-05-20 Vineet Gupta New
[v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] [v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - - --- 2024-05-20 Vineet Gupta New
RISC-V: propgue/epilogue expansion code minor changes [NFC] RISC-V: propgue/epilogue expansion code minor changes [NFC] - - - - --- 2024-05-15 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const materialization ... [part of PR/106265] [COMMITTED] RISC-V: avoid LUI based const materialization ... [part of PR/106265] - - - 1 --- 2024-05-14 Vineet Gupta New
[v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-05-13 Vineet Gupta New
[v2,1/2] RISC-V: avoid LUI based const materialization ... [part of PR/106265] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-05-13 Vineet Gupta New
[Committed,2/2] RISC-V: miscll comment fixes [NFC] [Committed,1/2] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-03 Vineet Gupta New
[Committed,1/2] docs: rtl: document GET_MODE_INNER [Committed,1/2] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-03 Vineet Gupta New
[v2,1/3] docs: rtl: document GET_MODE_INNER [v2,1/3] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-02 Vineet Gupta New
[3/3] combine: initialize a local var Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[2/3] RISC-V: miscll comment fixes [NFC] Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[1/3] docs: rtl: document GET_MODE_INNER Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[COMMITTED] RISC-V: testsuite: ensure vtype is call clobbered [COMMITTED] RISC-V: testsuite: ensure vtype is call clobbered - - - - --- 2024-03-28 Vineet Gupta New
RISC-V: testsuite: ensure vtype is call clobbered RISC-V: testsuite: ensure vtype is call clobbered - - - - --- 2024-03-27 Vineet Gupta New
[gcc-15,3/3] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[gcc-15,2/3] RISC-V: avoid LUI based const mat: keep stack offsets aligned RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[gcc-15,1/3] RISC-V: avoid LUI based const materialization ... [part of PR/106265] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-17 Vineet Gupta New
[COMITTED,2/2] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-17 Vineet Gupta New
RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] - - - - --- 2024-01-16 Vineet Gupta New
[v2] RISC-V: RVV: add toggle to control vsetvl pass behavior [v2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-16 Vineet Gupta New
RISC-V: RVV: add toggle to control vsetvl pass behavior RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2023-12-22 Vineet Gupta New
[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] [Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - 1 - - --- 2023-11-15 Vineet Gupta New
[Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1 --- 2023-11-15 Vineet Gupta New
RISC-V: fix vsetvli pass testsuite failure [PR/112447] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - 2 - - --- 2023-11-15 Vineet Gupta New
[RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - - --- 2023-11-15 Vineet Gupta New
[[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls [[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - 1 - 1 --- 2023-11-01 Vineet Gupta New
RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - - - 1 --- 2023-10-31 Vineet Gupta New
[v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1 --- 2023-10-30 Vineet Gupta New
[v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - - --- 2023-10-30 Vineet Gupta New
[RFC] RISC-V: elide sign extend when expanding cmp_and_jump [RFC] RISC-V: elide sign extend when expanding cmp_and_jump - - - - --- 2023-10-25 Vineet Gupta New
[COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output [COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output - - - - --- 2023-10-17 Vineet Gupta New
[v2] RISC-V/testsuite/pr111466.c: update test and expected output [v2] RISC-V/testsuite/pr111466.c: update test and expected output - - - - --- 2023-10-17 Vineet Gupta New
RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W - - - - --- 2023-10-17 Vineet Gupta New
[COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests [COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - - --- 2023-10-16 Vineet Gupta New
RISC-V/testsuite: add a default march (lacking zfa) to some fp tests RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - - --- 2023-10-15 Vineet Gupta New
[COMMITTED] RISC-V: const: hide mvconst splitter from IRA [COMMITTED] RISC-V: const: hide mvconst splitter from IRA - - - - --- 2023-10-06 Vineet Gupta New
[v2] RISC-V: const: hide mvconst splitter from IRA [v2] RISC-V: const: hide mvconst splitter from IRA - - - - --- 2023-10-06 Vineet Gupta New
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