Show patches with: Submitter = Michael Meissner       |    State = Action Required       |    Archived = No       |   449 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[V5,2/2] PR target/105325: Fix memory constraints for power10 fusion. PR target/105325: Fix constraint issue with power10 fusion - - - - --- 2023-05-10 Michael Meissner New
[V4] PR target/105325, Make load/cmp fusion know about prefixed loads. [V4] PR target/105325, Make load/cmp fusion know about prefixed loads. - - - - --- 2023-04-26 Michael Meissner New
[V3] PR target/70243 - Do not generate vmaddfp or vnmsubdp [V3] PR target/70243 - Do not generate vmaddfp or vnmsubdp - - - - --- 2023-04-08 Michael Meissner New
[V2] PR target/70243: Do not generate vmaddfp and vnmsubfp [V2] PR target/70243: Do not generate vmaddfp and vnmsubfp - - - - --- 2023-04-07 Michael Meissner New
PR target/70243: Do not generate fmaddfp and fnmsubfp PR target/70243: Do not generate fmaddfp and fnmsubfp - - - - --- 2023-04-06 Michael Meissner New
[V3] PR target/105325, Make load/cmp fusion know about prefixed loads [V3] PR target/105325, Make load/cmp fusion know about prefixed loads - - - - --- 2023-03-28 Michael Meissner New
[V2] PR target/105325, Make load/cmp fusion know about prefixed load [V2] PR target/105325, Make load/cmp fusion know about prefixed load - - - - --- 2023-03-24 Michael Meissner New
PR target/105325, Make load/cmp fusion know about prefixed loads PR target/105325, Make load/cmp fusion know about prefixed loads - - - - --- 2023-03-21 Michael Meissner New
[V4] Rework 128-bit complex multiply and divide. [V4] Rework 128-bit complex multiply and divide. - - - - --- 2023-03-10 Michael Meissner New
[8/8] Add saturating subtract built-ins. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[7/8] Support load/store vector with right length. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[6/8] PowerPC: Add support for 1,024 bit DMR registers. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[4/8] PowerPC: Switch to dense math names for all MMA operations PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[3/8] PowerPC: Make MMA insns support DMR registers. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[2/8] PowerPC: Add support for accumulators in DMR registers. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[1/8] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair [1/8] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair - - - - --- 2023-02-03 Michael Meissner New
[1/8] PowerPC: Add -mcpu=future. PowerPC future support for Dense Math - - - - --- 2023-02-03 Michael Meissner New
[2/2] Rework 128-bit complex multiply and divide. Repost of patches for solving the build on Fedora 36 problem - - - - --- 2023-02-03 Michael Meissner New
[1/2] PR target/107299: Fix build issue when long double is IEEE 128-bit Repost of patches for solving the build on Fedora 36 problem - - - - --- 2023-02-03 Michael Meissner New
Bump up precision size to 16 bits. Bump up precision size to 16 bits. - - - - --- 2023-02-02 Michael Meissner New
PR target/107299: Fix build issue when long double is IEEE 128-bit PR target/107299: Fix build issue when long double is IEEE 128-bit - - - - --- 2023-01-19 Michael Meissner New
[3/3,V3] PR 107299, Update float 128-bit conversion [1/3,V3] PR 107299, Rework 128-bit complex multiply and divide - - - - --- 2022-12-14 Michael Meissner New
[2/3,V3] PR 107299, Make __float128 use the _Float128 type [1/3,V3] PR 107299, Rework 128-bit complex multiply and divide - - - - --- 2022-12-14 Michael Meissner New
[1/3,V3] PR 107299, Rework 128-bit complex multiply and divide [1/3,V3] PR 107299, Rework 128-bit complex multiply and divide - - - - --- 2022-12-14 Michael Meissner New
[V2] Rework 128-bit complex multiply and divide, PR target/107299 [V2] Rework 128-bit complex multiply and divide, PR target/107299 - - - - --- 2022-12-13 Michael Meissner New
[8] PowerPC: Support load/store vector with right length. [8] PowerPC: Support load/store vector with right length. - - - - --- 2022-11-12 Michael Meissner New
[7] PowerPC: Add -mcpu=future saturating subtract built-ins. [7] PowerPC: Add -mcpu=future saturating subtract built-ins. - - - - --- 2022-11-12 Michael Meissner New
[6/6] PowerPC: Add support for 1,024 bit DMR registers. PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[5/6] PowerPC: Switch to dense math names for all MMA operations. PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[4/6] PowerPC: Make MMA insns support DMR registers PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[3/6] PowerPC: Add support for accumulators in DMR registers. PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair. PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[1/6] PowerPC: Add -mcpu=future PowerPC Dense Math prelimary support (-mcpu=future) - - - - --- 2022-11-10 Michael Meissner New
[3/3] Update float 128-bit conversions, PR target/107299. [1/3] Rework 128-bit complex multiply and divide, PR target/107299 - - - - --- 2022-11-02 Michael Meissner New
[2/3] Make __float128 use the _Float128 type, PR target/107299 [1/3] Rework 128-bit complex multiply and divide, PR target/107299 - - - - --- 2022-11-02 Michael Meissner New
[1/3] Rework 128-bit complex multiply and divide, PR target/107299 [1/3] Rework 128-bit complex multiply and divide, PR target/107299 - - - - --- 2022-11-02 Michael Meissner New
Update float 128-bit conversions Update float 128-bit conversions - - - - --- 2022-09-12 Michael Meissner New
Update float 128-bit conversions Update float 128-bit conversions - - - - --- 2022-09-08 Michael Meissner New
Improve converting between 128-bit modes that use the same format Improve converting between 128-bit modes that use the same format - - - - --- 2022-08-18 Michael Meissner New
Rework 128-bit complex multiply and divide. Rework 128-bit complex multiply and divide. - - - - --- 2022-08-18 Michael Meissner New
[3/3] Add 'w' suffix for __ibm128 constants Improvements to __ibm128 on PowerPC - - - - --- 2022-08-18 Michael Meissner New
[2/3] Allow __ibm128 with -msoft-float (PR target/105334) Improvements to __ibm128 on PowerPC - - - - --- 2022-08-18 Michael Meissner New
[1/3] Allow __ibm128 even if IEEE 128-bit floating point is not supported. Improvements to __ibm128 on PowerPC - - - - --- 2022-08-18 Michael Meissner New
[5/5] Support IEEE 128-bit overload test data built-in functions. IEEE 128-bit built-in overload support. - - - - --- 2022-07-28 Michael Meissner New
[4/5] Support IEEE 128-bit overload extract and insert built-in functions. IEEE 128-bit built-in overload support. - - - - --- 2022-07-28 Michael Meissner New
[3/5] Support IEEE 128-bit overload comparison built-in functions. IEEE 128-bit built-in overload support. - - - - --- 2022-07-28 Michael Meissner New
[2/5] Support IEEE 128-bit overload round_to_odd built-in functions. IEEE 128-bit built-in overload support. - - - - --- 2022-07-28 Michael Meissner New
[1/5] IEEE 128-bit built-in overload support. IEEE 128-bit built-in overload support. - - - - --- 2022-07-28 Michael Meissner New
[V2] Do not enable -mblock-ops-vector-pair. [V2] Do not enable -mblock-ops-vector-pair. - - - - --- 2022-07-25 Michael Meissner New
Remove setting -mblock-ops-vector-pair on power10. Remove setting -mblock-ops-vector-pair on power10. - - - - --- 2022-07-21 Michael Meissner New
[V2] Disable generating load/store vector pairs for block copies. [V2] Disable generating load/store vector pairs for block copies. - - - - --- 2022-06-10 Michael Meissner New
[3/3] Adjust MMA tests to account for no store vector pair. Disable generating store vector pair. - - - - --- 2022-06-07 Michael Meissner New
[2/3] Disable generating load/store vector pairs for block copies. Disable generating store vector pair. - - - - --- 2022-06-07 Michael Meissner New
[1/3] Disable generating store vector pair. Disable generating store vector pair. - - - - --- 2022-06-07 Michael Meissner New
[V3] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293 [V3] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293 - - - - --- 2022-06-07 Michael Meissner New
Generate vadduqm and vsubuqm for TImode add/subtract Generate vadduqm and vsubuqm for TImode add/subtract - - - - --- 2022-05-13 Michael Meissner New
Optimize multiply/add of DImode extended to TImode, PR target/103109. Optimize multiply/add of DImode extended to TImode, PR target/103109. - - - - --- 2022-05-13 Michael Meissner New
Add zero_extendditi2. Improve lxvr*x code generation. Add zero_extendditi2. Improve lxvr*x code generation. - - - - --- 2022-05-13 Michael Meissner New
Delay splitting addti3/subti3 until first split pass. Delay splitting addti3/subti3 until first split pass. - - - - --- 2022-05-13 Michael Meissner New
Replace UNSPEC with RTL code for extendditi2. Replace UNSPEC with RTL code for extendditi2. - - - - --- 2022-05-13 Michael Meissner New
Optimize vec_splats of constant V2DI/V2DF vec_extract, PR target/99293 Optimize vec_splats of constant V2DI/V2DF vec_extract, PR target/99293 - - - - --- 2022-05-13 Michael Meissner New
Remove -mpower8-fusion options Remove -mpower8-fusion options - - - - --- 2022-05-12 Michael Meissner New
[V4] Eliminate power8 fusion options, use power8 tuning, PR target/102059 [V4] Eliminate power8 fusion options, use power8 tuning, PR target/102059 - - - - --- 2022-04-13 Michael Meissner New
[V3] Eliminate power8 fusion options, use power8 tuning, PR target/102059 [V3] Eliminate power8 fusion options, use power8 tuning, PR target/102059 - - - - --- 2022-04-07 Michael Meissner New
Committed: [PATCH] Disable float128 tests on VxWorks, PR target/104253. Committed: [PATCH] Disable float128 tests on VxWorks, PR target/104253. - - - - --- 2022-04-07 Michael Meissner New
Disable float128 tests on VxWorks, PR target/104253. Disable float128 tests on VxWorks, PR target/104253. - - - - --- 2022-04-07 Michael Meissner New
Add zero_extendditi2. Improve lxvr*x code generation. Add zero_extendditi2. Improve lxvr*x code generation. - - - - --- 2022-04-06 Michael Meissner New
Replace UNSPEC with RTL code for extendditi2. Replace UNSPEC with RTL code for extendditi2. - - - - --- 2022-04-01 Michael Meissner New
[V2] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293. [V2] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293. - - - - --- 2022-03-30 Michael Meissner New
[4/4] Allow vsx_extract_<mode> to use Altivec registers, PR target/99293 Optimize vec_splats of vec_extract, PR target/99293 - - - - --- 2022-03-28 Michael Meissner New
[3/4] Make vsx_extract_<mode> use correct insn attributes, PR target 99293. Optimize vec_splats of vec_extract, PR target/99293 - - - - --- 2022-03-28 Michael Meissner New
[2/4] Make vsx_splat_<mode>_reg use correct insn attributes, PR target/99293 Optimize vec_splats of vec_extract, PR target/99293 - - - - --- 2022-03-28 Michael Meissner New
[1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293. Optimize vec_splats of vec_extract, PR target/99293 - - - - --- 2022-03-28 Michael Meissner New
[BACKPORT] Backport PR fortran/96983 fix to GCC 11 [BACKPORT] Backport PR fortran/96983 fix to GCC 11 - - - - --- 2022-03-17 Michael Meissner New
Fix DImode to TImode sign extend issue, PR target/104868 Fix DImode to TImode sign extend issue, PR target/104868 - - - - --- 2022-03-11 Michael Meissner New
[V2] Eliminate power8 fusion options, use power8 tuning, PR target/102059 [V2] Eliminate power8 fusion options, use power8 tuning, PR target/102059 - - - - --- 2022-03-10 Michael Meissner New
[COMMITTED] Optimize signed DImode -> TImode on power10. [COMMITTED] Optimize signed DImode -> TImode on power10. - - - - --- 2022-03-05 Michael Meissner New
[V2] Optimize signed DImode -> TImode on power10, PR target/104698 [V2] Optimize signed DImode -> TImode on power10, PR target/104698 - - - - --- 2022-03-02 Michael Meissner New
Optimize signed DImode -> TImode on power10, PR target/104698 Optimize signed DImode -> TImode on power10, PR target/104698 - - - - --- 2022-03-01 Michael Meissner New
Don't do int cmoves for IEEE comparisons, PR target/104256. Don't do int cmoves for IEEE comparisons, PR target/104256. - - - - --- 2022-02-17 Michael Meissner New
[V3] PR target/99708- Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__ [V3] PR target/99708- Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__ - - - - --- 2022-02-16 Michael Meissner New
, PR target/99708 - Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__ , PR target/99708 - Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__ - - - - --- 2022-02-15 Michael Meissner New
PR target/102059 Fix inline of target specific functions PR target/102059 Fix inline of target specific functions - - - - --- 2022-02-09 Michael Meissner New
[V2] Use system default for long double if not specified on PowerPC. [V2] Use system default for long double if not specified on PowerPC. - - - - --- 2022-02-04 Michael Meissner New
Ping: [PATCH] Use system default for long double if not specified on PowerPC. Ping: [PATCH] Use system default for long double if not specified on PowerPC. - - - - --- 2022-01-31 Michael Meissner New
, PR 104253, Fix __ibm128 conversions on IEEE 128-bit system , PR 104253, Fix __ibm128 conversions on IEEE 128-bit system - - - - --- 2022-01-29 Michael Meissner New
Ping, important: [PATCH] Use system default for long double if not specified on PowerPC. Ping, important: [PATCH] Use system default for long double if not specified on PowerPC. - - - - --- 2022-01-21 Michael Meissner New
Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136 Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136 - - - - --- 2022-01-21 Michael Meissner New
Use system default for long double if not specified on PowerPC. Use system default for long double if not specified on PowerPC. - - - - --- 2022-01-12 Michael Meissner New
Allow other languages to change long double format on PowerPC Allow other languages to change long double format on PowerPC - - - - --- 2022-01-12 Michael Meissner New
PR 102935, Fix pr101384-1.c code generation test. PR 102935, Fix pr101384-1.c code generation test. - - - - --- 2022-01-08 Michael Meissner New
PR 103763, Fix fold-vec-splat-floatdouble on power10. PR 103763, Fix fold-vec-splat-floatdouble on power10. - - - - --- 2022-01-07 Michael Meissner New
[3/3] Use absolute switch table addresses for zero cycle moves. Add zero cycle move support - - - - --- 2021-11-19 Michael Meissner New
[2/3] Set power10 fusion if -mtune=power10. Add zero cycle move support - - - - --- 2021-11-19 Michael Meissner New
[1/3] Add power10 zero cycle moves for switches & indirect jumps Add zero cycle move support - - - - --- 2021-11-19 Michael Meissner New
[5/5] Add Power10 XXSPLTIDP for SFmode/DFmode constants. Add Power10 XXSPLTI* and LXVKQ instructions - - - - --- 2021-11-05 Michael Meissner New
[4/5] Add Power10 XXSPLTIDP for vector constants Add Power10 XXSPLTI* and LXVKQ instructions - - - - --- 2021-11-05 Michael Meissner New
[3/5] Add Power10 XXSPLTIW Add Power10 XXSPLTI* and LXVKQ instructions - - - - --- 2021-11-05 Michael Meissner New
[2/5] Add Power10 XXSPLTI* and LXVKQ instructions (LXVKQ) Add Power10 XXSPLTI* and LXVKQ instructions - - - - --- 2021-11-05 Michael Meissner New
[1/5] Add XXSPLTI* and LXVKQ instructions (new data structure and function) Add Power10 XXSPLTI* and LXVKQ instructions - - - - --- 2021-11-05 Michael Meissner New
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