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[V2,0/3] RISC-V: Add an experimental vector calling convention

Message ID 20230810070345.1623064-1-lehua.ding@rivai.ai
Headers show
Series RISC-V: Add an experimental vector calling convention | expand

Message

Lehua Ding Aug. 10, 2023, 7:03 a.m. UTC 
Hi RISC-V folks,

This patch implement the proposal of RISC-V vector calling convention[1] and
this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
all vector type arguments and return values are pass by reference. With this
patch, these arguments and return values can pass through vector registers.
Currently only vector types defined in the RISC-V Vector Extension Intrinsic Document[2]
are supported. GNU-ext vector types are unsupported for now since the
corresponding proposal was not presented.

The proposal introduce a new calling convention variant, functions which follow
this variant need follow the bellow vector register convention.

| Name    | ABI Mnemonic | Meaning                      | Preserved across calls?
=================================================================================
| v0      |              | Argument register            | No
| v1-v7   |              | Callee-saved registers       | Yes
| v8-v23  |              | Argument registers           | No
| v24-v31 |              | Callee-saved registers       | Yes

If a functions follow this vector calling convention, then the function symbole
must be annotated with .variant_cc directive[3] (used to indicate that it is a
calling convention variant).

This implementation split into three parts, each part corresponds to a sub-patch.

- Part-1: Select suitable vector regsiters for vector type arguments and return
  values according to the proposal.
- Part-2: Allocate frame area for callee-saved vector registers and save/restore
  them in prologue and epilogue.
- Part-3: Generate .variant_cc directive for vector function in assembly code.

Best,
Lehua

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
[2] https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
[3] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops

Lehua Ding (3):
  RISC-V: Part-1: Select suitable vector registers for vector type args
    and returns
  RISC-V: Part-2: Save/Restore vector registers which need to be
    preversed
  RISC-V: Part-3: Output .variant_cc directive for vector function

 gcc/config/riscv/riscv-protos.h               |   4 +
 gcc/config/riscv/riscv-sr.cc                  |  12 +-
 gcc/config/riscv/riscv-vector-builtins.cc     |  10 +
 gcc/config/riscv/riscv.cc                     | 505 ++++++++++++++++--
 gcc/config/riscv/riscv.h                      |  40 ++
 gcc/config/riscv/riscv.md                     |  43 +-
 gcc/config/riscv/riscv.opt                    |   5 +
 .../riscv/rvv/base/abi-call-args-1-run.c      | 127 +++++
 .../riscv/rvv/base/abi-call-args-1.c          | 197 +++++++
 .../riscv/rvv/base/abi-call-args-2-run.c      |  34 ++
 .../riscv/rvv/base/abi-call-args-2.c          |  27 +
 .../riscv/rvv/base/abi-call-args-3-run.c      | 260 +++++++++
 .../riscv/rvv/base/abi-call-args-3.c          | 116 ++++
 .../riscv/rvv/base/abi-call-args-4-run.c      | 145 +++++
 .../riscv/rvv/base/abi-call-args-4.c          | 111 ++++
 .../riscv/rvv/base/abi-call-error-1.c         |  11 +
 .../riscv/rvv/base/abi-call-return-run.c      | 127 +++++
 .../riscv/rvv/base/abi-call-return.c          | 197 +++++++
 .../riscv/rvv/base/abi-call-variant_cc.c      |  39 ++
 .../rvv/base/abi-callee-saved-1-fixed-1.c     |  85 +++
 .../rvv/base/abi-callee-saved-1-fixed-2.c     |  85 +++
 .../riscv/rvv/base/abi-callee-saved-1.c       |  87 +++
 .../riscv/rvv/base/abi-callee-saved-2.c       | 117 ++++
 23 files changed, 2322 insertions(+), 62 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c

Comments

Richard Biener Aug. 10, 2023, 7:43 a.m. UTC | #1 
On Thu, Aug 10, 2023 at 9:04 AM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
> Hi RISC-V folks,
>
> This patch implement the proposal of RISC-V vector calling convention[1] and
> this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
> all vector type arguments and return values are pass by reference. With this
> patch, these arguments and return values can pass through vector registers.
> Currently only vector types defined in the RISC-V Vector Extension Intrinsic Document[2]
> are supported. GNU-ext vector types are unsupported for now since the
> corresponding proposal was not presented.
>
> The proposal introduce a new calling convention variant, functions which follow
> this variant need follow the bellow vector register convention.
>
> | Name    | ABI Mnemonic | Meaning                      | Preserved across calls?
> =================================================================================
> | v0      |              | Argument register            | No
> | v1-v7   |              | Callee-saved registers       | Yes
> | v8-v23  |              | Argument registers           | No
> | v24-v31 |              | Callee-saved registers       | Yes
>
> If a functions follow this vector calling convention, then the function symbole
> must be annotated with .variant_cc directive[3] (used to indicate that it is a
> calling convention variant).
>
> This implementation split into three parts, each part corresponds to a sub-patch.
>
> - Part-1: Select suitable vector regsiters for vector type arguments and return
>   values according to the proposal.
> - Part-2: Allocate frame area for callee-saved vector registers and save/restore
>   them in prologue and epilogue.
> - Part-3: Generate .variant_cc directive for vector function in assembly code.

Just to mention at some point you want to think about the OpenMP SIMD ABI which
includes a mangling scheme but would also open up to have different
calling conventions.
So please keep that usage case in mind, possibly allowing the vector
calling convention
to be required for this.  Also note there's 'inbranch' variants which
require passing
a mask - your table above doesn't list any mask registers (in case
those exist in RISC-V).

Richard.

> Best,
> Lehua
>
> [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
> [2] https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
> [3] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
>
> Lehua Ding (3):
>   RISC-V: Part-1: Select suitable vector registers for vector type args
>     and returns
>   RISC-V: Part-2: Save/Restore vector registers which need to be
>     preversed
>   RISC-V: Part-3: Output .variant_cc directive for vector function
>
>  gcc/config/riscv/riscv-protos.h               |   4 +
>  gcc/config/riscv/riscv-sr.cc                  |  12 +-
>  gcc/config/riscv/riscv-vector-builtins.cc     |  10 +
>  gcc/config/riscv/riscv.cc                     | 505 ++++++++++++++++--
>  gcc/config/riscv/riscv.h                      |  40 ++
>  gcc/config/riscv/riscv.md                     |  43 +-
>  gcc/config/riscv/riscv.opt                    |   5 +
>  .../riscv/rvv/base/abi-call-args-1-run.c      | 127 +++++
>  .../riscv/rvv/base/abi-call-args-1.c          | 197 +++++++
>  .../riscv/rvv/base/abi-call-args-2-run.c      |  34 ++
>  .../riscv/rvv/base/abi-call-args-2.c          |  27 +
>  .../riscv/rvv/base/abi-call-args-3-run.c      | 260 +++++++++
>  .../riscv/rvv/base/abi-call-args-3.c          | 116 ++++
>  .../riscv/rvv/base/abi-call-args-4-run.c      | 145 +++++
>  .../riscv/rvv/base/abi-call-args-4.c          | 111 ++++
>  .../riscv/rvv/base/abi-call-error-1.c         |  11 +
>  .../riscv/rvv/base/abi-call-return-run.c      | 127 +++++
>  .../riscv/rvv/base/abi-call-return.c          | 197 +++++++
>  .../riscv/rvv/base/abi-call-variant_cc.c      |  39 ++
>  .../rvv/base/abi-callee-saved-1-fixed-1.c     |  85 +++
>  .../rvv/base/abi-callee-saved-1-fixed-2.c     |  85 +++
>  .../riscv/rvv/base/abi-callee-saved-1.c       |  87 +++
>  .../riscv/rvv/base/abi-callee-saved-2.c       | 117 ++++
>  23 files changed, 2322 insertions(+), 62 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
>
> --
> 2.36.3
>
Lehua Ding Aug. 10, 2023, 8:08 a.m. UTC | #2 
Hi Richard,


Thanks review.


&gt; Just to mention at some point you want to think about the OpenMP SIMD ABI which
&gt; includes a mangling scheme but would also open up to have different
&gt; calling conventions.&gt; So please keep that usage case in mind, possibly allowing the vector
&gt; calling convention
&gt; to be required for this.&nbsp;&nbsp;


Thanks remainder.&nbsp;A new function attribute `riscv_vector_cc` will be introduced
later to specify that a function adheres to the vector calling convention.

&gt; Also note there's 'inbranch' variants which
&gt; require passing
&gt; a mask - your table above doesn't list any mask registers (in case
&gt; those exist in RISC-V).


Separate mask registers do not exist in RISC-V;
mask arguments share vector registers.

Best,
Lehua