| Message ID | 20240527-algebra-pencil-c12962d62468@wendy |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | PCI: microchip: support using either instance 1 or 2 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 26 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 27/05/2024 11:37, Conor Dooley wrote: > The PCI host controller on PolarFire SoC has multiple "instances", each > with their own bridge and ctrl address spaces. The original binding has > an "apb" register region, and it is expected to be set to the base > address of the host controllers register space. Some defines in the > Linux driver were used to compute the addresses of the bridge and ctrl > address ranges corresponding to instance1. Some customers want to use > instance2 however and that requires changing the defines in the driver, > which is clearly not a portable solution. > > Remove this "apb" register region from the binding and add "bridge" & > "ctrl" regions instead, that will directly communicate the address of > these regions > > Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../devicetree/bindings/pci/microchip,pcie-host.yaml | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 5d7aec5f54e71..45c14b6e4aa41 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -18,12 +18,13 @@ properties: const: microchip,pcie-host-1.0 # PolarFire reg: - maxItems: 2 + maxItems: 3 reg-names: items: - const: cfg - - const: apb + - const: bridge + - const: ctrl clocks: description: @@ -115,8 +116,9 @@ examples: pcie0: pcie@2030000000 { compatible = "microchip,pcie-host-1.0"; reg = <0x0 0x70000000 0x0 0x08000000>, - <0x0 0x43000000 0x0 0x00010000>; - reg-names = "cfg", "apb"; + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>;
The PCI host controller on PolarFire SoC has multiple "instances", each with their own bridge and ctrl address spaces. The original binding has an "apb" register region, and it is expected to be set to the base address of the host controllers register space. Some defines in the Linux driver were used to compute the addresses of the bridge and ctrl address ranges corresponding to instance1. Some customers want to use instance2 however and that requires changing the defines in the driver, which is clearly not a portable solution. Remove this "apb" register region from the binding and add "bridge" & "ctrl" regions instead, that will directly communicate the address of these regions Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)