| Message ID | 1712036704-21064-2-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add i.MX8Q HSIO PHY driver support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success |
On Tue, Apr 02, 2024 at 01:45:02PM +0800, Richard Zhu wrote: > Add binding for controller ID and HSIO configuration setting of the > i.MX8Q HSIO SerDes PHY. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h > index 8bbe2d6538d8..3292c8be3354 100644 > --- a/include/dt-bindings/phy/phy-imx8-pcie.h > +++ b/include/dt-bindings/phy/phy-imx8-pcie.h > @@ -11,4 +11,33 @@ > #define IMX8_PCIE_REFCLK_PAD_INPUT 1 > #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 > > +/* > + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: > + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one capable > + * lane) and SATA. > + * > + * In the different use cases. PCIEA can be binded to PHY lane0, lane1 s/binded/bound/ And throughout your patches. > + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA > + * can only be binded to last lane2 PHY. > + * > + * Define i.MX8Q HSIO controller ID here to specify the controller > + * binded to the PHY. > + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only > + * support one lane) controller. > + */ > +#define IMX8Q_HSIO_PCIEA_ID 0 > +#define IMX8Q_HSIO_PCIEB_ID 1 > +#define IMX8Q_HSIO_SATA_ID 2 Please use the standard phy mode defines. > + > +/* > + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. > + * Define configurations beside PCIEA is enabled. > + * > + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. > + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. > + */ > +#define IMX8Q_HSIO_CFG_SATA 1 > +#define IMX8Q_HSIO_CFG_PCIEB 2 > +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 This seems somewhat redundant both as the 3rd define is just an OR of the first 2 and all 3 overlap with the prior defines. Seems like with standard PHY modes, the only additional information you might need is PCIEB vs. PCIEA. Rob
diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h index 8bbe2d6538d8..3292c8be3354 100644 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -11,4 +11,33 @@ #define IMX8_PCIE_REFCLK_PAD_INPUT 1 #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 +/* + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one + * lane) and SATA. + * + * In the different use cases. PCIEA can be binded to PHY lane0, lane1 + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA + * can only be binded to last lane2 PHY. + * + * Define i.MX8Q HSIO controller ID here to specify the controller + * binded to the PHY. + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only + * support one lane) controller. + */ +#define IMX8Q_HSIO_PCIEA_ID 0 +#define IMX8Q_HSIO_PCIEB_ID 1 +#define IMX8Q_HSIO_SATA_ID 2 + +/* + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. + * Define configurations beside PCIEA is enabled. + * + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. + */ +#define IMX8Q_HSIO_CFG_SATA 1 +#define IMX8Q_HSIO_CFG_PCIEB 2 +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 + #endif /* _DT_BINDINGS_IMX8_PCIE_H */