From patchwork Tue Apr 2 05:45:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 1918650 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-55270-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V7y3623Gdz1yZ3 for ; Tue, 2 Apr 2024 17:02:42 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id B9985283087 for ; Tue, 2 Apr 2024 06:02:40 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACD9F1F958; Tue, 2 Apr 2024 06:02:20 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FFD11B809; Tue, 2 Apr 2024 06:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712037740; cv=none; b=FcKrGEKff77eI6qVAQerJN+DrMWMYtpIZIpo5BYN7ugRXPkg818ZCUfYw2qTL16psmkqeTVBGuJ6yfnAQ8+VGXilcD/wpqOvf5DRzHbtlBz6c9L5cgcXjSCFSb6sPZA1F0JvuIpG/yRlk7i8HvTOAcT0/mReBQU0nXWObRXOHNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712037740; c=relaxed/simple; bh=uRNKhWnzWVII8HFWbPeoAJ1s5eGvNj4lNd8CFYF5wSw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=DOQn/53r3n/q8r9ZcQZGOTPJxR5f9+Eo4S4It9OQhvCKQKiEMyYkb+FB30Jt2RSYkne9yHY084ceD+6LPYdeZBZR8mghsQCvKPpu2m5J8W9rZQipFWKSiKJpEy9N5GO8KUV0GkwxnY8WSINWm6BBYwhcpR0mK0Sm4T7deJ00Esg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C35441A19BB; Tue, 2 Apr 2024 08:02:16 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 798EA1A19B8; Tue, 2 Apr 2024 08:02:16 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 92ABE180031D; Tue, 2 Apr 2024 14:02:14 +0800 (+08) From: Richard Zhu To: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v2 1/3] dt-bindings: phy: phy-imx8-pcie: Add binding for i.MX8Q HSIO SerDes PHY Date: Tue, 2 Apr 2024 13:45:02 +0800 Message-Id: <1712036704-21064-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com> References: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add binding for controller ID and HSIO configuration setting of the i.MX8Q HSIO SerDes PHY. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h index 8bbe2d6538d8..3292c8be3354 100644 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -11,4 +11,33 @@ #define IMX8_PCIE_REFCLK_PAD_INPUT 1 #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 +/* + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one + * lane) and SATA. + * + * In the different use cases. PCIEA can be binded to PHY lane0, lane1 + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA + * can only be binded to last lane2 PHY. + * + * Define i.MX8Q HSIO controller ID here to specify the controller + * binded to the PHY. + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only + * support one lane) controller. + */ +#define IMX8Q_HSIO_PCIEA_ID 0 +#define IMX8Q_HSIO_PCIEB_ID 1 +#define IMX8Q_HSIO_SATA_ID 2 + +/* + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. + * Define configurations beside PCIEA is enabled. + * + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. + */ +#define IMX8Q_HSIO_CFG_SATA 1 +#define IMX8Q_HSIO_CFG_PCIEB 2 +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 + #endif /* _DT_BINDINGS_IMX8_PCIE_H */ From patchwork Tue Apr 2 05:45:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 1918651 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 408B12011F9; Tue, 2 Apr 2024 08:02:18 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id AD38A201CA7; Tue, 2 Apr 2024 08:02:17 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C69E5183AD14; Tue, 2 Apr 2024 14:02:15 +0800 (+08) From: Richard Zhu To: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v2 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding Date: Tue, 2 Apr 2024 13:45:03 +0800 Message-Id: <1712036704-21064-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com> References: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. - Use the controller ID to specify which controller is binded to the PHY. - Introduce one HSIO configuration, mandatory required to set "PCIE_AB_SELECT" and "PHY_X1_EPCS_SEL" during the initialization. Signed-off-by: Richard Zhu --- .../bindings/phy/fsl,imx8q-hsio.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml new file mode 100644 index 000000000000..506551d4d94a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8q-hsio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8Q SoC series HSIO SERDES PHY + +maintainers: + - Richard Zhu + +properties: + compatible: + enum: + - fsl,imx8qxp-serdes + - fsl,imx8qm-serdes + reg: + minItems: 4 + maxItems: 4 + + "#phy-cells": + const: 3 + description: | + The first number defines the ID of the PHY contained in the HSIO macro. + The second defines controller ID binded to the PHY. The third defines the + HSIO configuratons refer to the different use cases. They are defined in + dt-bindings/phy/phy-imx8-pcie.h + + reg-names: + items: + - const: reg + - const: phy + - const: ctrl + - const: misc + + clocks: + minItems: 5 + maxItems: 14 + + clock-names: + minItems: 5 + maxItems: 14 + + fsl,refclk-pad-mode: + description: | + Specifies the mode of the refclk pad used. It can be UNUSED(PHY + refclock is derived from SoC internal source), INPUT(PHY refclock + is provided externally via the refclk pad) or OUTPUT(PHY refclock + is derived from SoC internal source and provided on the refclk pad). + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants + to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + power-domains: + description: | + i.MX8Q HSIO SerDes power domains. i.MX8QXP has one SerDes power domains. + And i.MX8QM has two. + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - fsl,refclk-pad-mode + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-serdes + then: + properties: + clock-names: + items: + - const: apb_pclk0 + - const: pclk0 + - const: phy0_crr + - const: ctl0_crr + - const: misc_crr + power-domains: + minItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-serdes + then: + properties: + clock-names: + items: + - const: pclk0 + - const: pclk1 + - const: apb_pclk0 + - const: apb_pclk1 + - const: pclk2 + - const: epcs_tx + - const: epcs_rx + - const: apb_pclk2 + - const: phy0_crr + - const: phy1_crr + - const: ctl0_crr + - const: ctl1_crr + - const: ctl2_crr + - const: misc_crr + power-domains: + minItems: 2 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + serdes: phy@5f1a0000 { + compatible = "fsl,imx8qxp-serdes"; + reg = <0x5f1a0000 0x10000>, + <0x5f120000 0x10000>, + <0x5f140000 0x10000>, + <0x5f160000 0x10000>; + reg-names = "reg", "phy", "ctrl", "misc"; + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_4>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names = "apb_pclk0", "pclk0", "phy0_crr", "ctl0_crr", + "misc_crr"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + #phy-cells = <3>; + status = "disabled"; + }; +...