| Message ID | 20220919164616.12492-1-macroalpha82@gmail.com |
|---|---|
| Headers | show |
| Series | rockchip-dsi for rk3568 | expand |
On 19-09-22, 11:46, Chris Morgan wrote: > From: Chris Morgan <macromorgan@hotmail.com> > > This series adds support for the dsi and dphy controllers on the > Rockchip RK3568. Applied 1,2, thanks
Hi Chris, Thanks for my comments into account! On 9/19/22 18:46, Chris Morgan wrote: > From: Chris Morgan <macromorgan@hotmail.com> > > This adds the DSI controller nodes and DSI-DPHY controller nodes to the > rk356x device tree. > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Michael Riesch <michael.riesch@wolfvision.net> Best regards, Michael > --- > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 80 ++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 319981c3e9f7..0473d7ee2668 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -699,6 +699,62 @@ vop_mmu: iommu@fe043e00 { > status = "disabled"; > }; > > + dsi0: dsi@fe060000 { > + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; > + reg = <0x00 0xfe060000 0x00 0x10000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "pclk", "hclk"; > + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; > + phy-names = "dphy"; > + phys = <&dsi_dphy0>; > + power-domains = <&power RK3568_PD_VO>; > + reset-names = "apb"; > + resets = <&cru SRST_P_DSITX_0>; > + rockchip,grf = <&grf>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dsi0_in: port@0 { > + reg = <0>; > + }; > + > + dsi0_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + dsi1: dsi@fe070000 { > + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; > + reg = <0x0 0xfe070000 0x0 0x10000>; > + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "pclk", "hclk"; > + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; > + phy-names = "dphy"; > + phys = <&dsi_dphy1>; > + power-domains = <&power RK3568_PD_VO>; > + reset-names = "apb"; > + resets = <&cru SRST_P_DSITX_1>; > + rockchip,grf = <&grf>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dsi1_in: port@0 { > + reg = <0>; > + }; > + > + dsi1_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > hdmi: hdmi@fe0a0000 { > compatible = "rockchip,rk3568-dw-hdmi"; > reg = <0x0 0xfe0a0000 0x0 0x20000>; > @@ -1594,6 +1650,30 @@ combphy2: phy@fe840000 { > status = "disabled"; > }; > > + dsi_dphy0: mipi-dphy@fe850000 { > + compatible = "rockchip,rk3568-dsi-dphy"; > + reg = <0x0 0xfe850000 0x0 0x10000>; > + clock-names = "ref", "pclk"; > + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; > + #phy-cells = <0>; > + power-domains = <&power RK3568_PD_VO>; > + reset-names = "apb"; > + resets = <&cru SRST_P_MIPIDSIPHY0>; > + status = "disabled"; > + }; > + > + dsi_dphy1: mipi-dphy@fe860000 { > + compatible = "rockchip,rk3568-dsi-dphy"; > + reg = <0x0 0xfe860000 0x0 0x10000>; > + clock-names = "ref", "pclk"; > + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; > + #phy-cells = <0>; > + power-domains = <&power RK3568_PD_VO>; > + reset-names = "apb"; > + resets = <&cru SRST_P_MIPIDSIPHY1>; > + status = "disabled"; > + }; > + > usb2phy0: usb2phy@fe8a0000 { > compatible = "rockchip,rk3568-usb2phy"; > reg = <0x0 0xfe8a0000 0x0 0x10000>;
On Mon, 19 Sep 2022 11:46:13 -0500, Chris Morgan wrote: > This series adds support for the dsi and dphy controllers on the > Rockchip RK3568. > > Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance. > > Changes since V3: > - Added labels to bindings in rk356x.dtsi file to make it easier to > reference in board dts files. > > [...] Applied, thanks! [3/3] arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x commit: e18d9b093006d8abd53e1ce13c0d5a8d0fcd5f64 Best regards,
From: Chris Morgan <macromorgan@hotmail.com> This series adds support for the dsi and dphy controllers on the Rockchip RK3568. Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance. Changes since V3: - Added labels to bindings in rk356x.dtsi file to make it easier to reference in board dts files. Changes since V2: - Removed dsi controller patches, as those have been merged upstream. - Removed notes about rolling back clock drivers. If I set the parent clock of the VOP port I'm using to VPLL and set the clock rate of PLL_VPLL to 500MHz this series works correctly for my panels without rolling anything back (per Heiko this is the correct way). - Added additional details about refactoring DPHY driver to add 2.5GHz for rk356x. All other devices still have a max speed of 1GHz. - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the phy_update_bits() works. Changes since RFCv1: - Identified cause of image shift (clock changes). - Noted that driver works now. - Added devicetree nodes for rk356x.dtsi. Chris Morgan (3): dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 phy/rockchip: inno-dsidphy: Add support for rk3568 arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 80 +++++++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++++++++++++++---- 3 files changed, 239 insertions(+), 46 deletions(-)