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[76.244.6.13]) by smtp.gmail.com with ESMTPSA id t184-20020a4a54c1000000b0044b0465bd07sm12501610ooa.20.2022.09.19.09.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 09:46:18 -0700 (PDT) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-phy@lists.infradead.org, jbx6244@gmail.com, cl@rock-chips.com, frank-w@public-files.de, s.hauer@pengutronix.de, michael.riesch@wolfvision.net, pgwipeout@gmail.com, heiko@sntech.de, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, vkoul@kernel.org, kishon@ti.com, Chris Morgan Subject: [PATCH v4 0/3] rockchip-dsi for rk3568 Date: Mon, 19 Sep 2022 11:46:13 -0500 Message-Id: <20220919164616.12492-1-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chris Morgan This series adds support for the dsi and dphy controllers on the Rockchip RK3568. Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance. Changes since V3: - Added labels to bindings in rk356x.dtsi file to make it easier to reference in board dts files. Changes since V2: - Removed dsi controller patches, as those have been merged upstream. - Removed notes about rolling back clock drivers. If I set the parent clock of the VOP port I'm using to VPLL and set the clock rate of PLL_VPLL to 500MHz this series works correctly for my panels without rolling anything back (per Heiko this is the correct way). - Added additional details about refactoring DPHY driver to add 2.5GHz for rk356x. All other devices still have a max speed of 1GHz. - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the phy_update_bits() works. Changes since RFCv1: - Identified cause of image shift (clock changes). - Noted that driver works now. - Added devicetree nodes for rk356x.dtsi. Chris Morgan (3): dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 phy/rockchip: inno-dsidphy: Add support for rk3568 arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 80 +++++++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++++++++++++++---- 3 files changed, 239 insertions(+), 46 deletions(-) Acked-by: Michael Riesch