| Message ID | 20220723215448.2532160-2-abel@x-silicon.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/2] package/llvm: Support for RISC-V on the LLVM package | expand |
Hello Abel, Le 23/07/2022 à 23:54, Abel Bernabeu a écrit : > This new setting will allow to test new toolchains already available > that support the vector extension (more patches coming soon). It seems that is the same series as v1: http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=* See 22.5.5. "Patch revision changelog" section for help. https://nightly.buildroot.org/manual.html#submitting-patches > > Signed-off-by: Abel Bernabeu <abel@x-silicon.com> > --- > arch/Config.in.riscv | 7 +++++++ > arch/arch.mk.riscv | 4 ++++ > 2 files changed, 11 insertions(+) > > diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv > index 288ed833eb..e4dc936cf8 100644 > --- a/arch/Config.in.riscv > +++ b/arch/Config.in.riscv > @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD > config BR2_RISCV_ISA_RVC > bool > > +config BR2_RISCV_ISA_RVV > + bool > + > choice > prompt "Target Architecture Variant" > default BR2_riscv_g > @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD > config BR2_RISCV_ISA_CUSTOM_RVC > bool "Compressed Instructions (C)" > select BR2_RISCV_ISA_RVC > + > +config BR2_RISCV_ISA_CUSTOM_RVV This option must depends on gcc-12. Best regards, Romain > + bool "Vector Instructions (V)" > + select BR2_RISCV_ISA_RVV > endif > > choice > diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv > index f3bf2b3467..07a94aa6a4 100644 > --- a/arch/arch.mk.riscv > +++ b/arch/arch.mk.riscv > @@ -26,5 +26,9 @@ endif > ifeq ($(BR2_RISCV_ISA_RVC),y) > GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c > endif > +ifeq ($(BR2_RISCV_ISA_RVV),y) > +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v > +endif > + > > endif
On 24/07/2022 10:08, Romain Naour wrote: > Hello Abel, > > Le 23/07/2022 à 23:54, Abel Bernabeu a écrit : >> This new setting will allow to test new toolchains already available >> that support the vector extension (more patches coming soon). > > It seems that is the same series as v1: > > http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=* > > See 22.5.5. "Patch revision changelog" section for help. > > https://nightly.buildroot.org/manual.html#submitting-patches > >> >> Signed-off-by: Abel Bernabeu <abel@x-silicon.com> >> --- >> arch/Config.in.riscv | 7 +++++++ >> arch/arch.mk.riscv | 4 ++++ >> 2 files changed, 11 insertions(+) >> >> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv >> index 288ed833eb..e4dc936cf8 100644 >> --- a/arch/Config.in.riscv >> +++ b/arch/Config.in.riscv >> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD >> config BR2_RISCV_ISA_RVC >> bool >> >> +config BR2_RISCV_ISA_RVV >> + bool >> + >> choice >> prompt "Target Architecture Variant" >> default BR2_riscv_g >> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD >> config BR2_RISCV_ISA_CUSTOM_RVC >> bool "Compressed Instructions (C)" >> select BR2_RISCV_ISA_RVC >> + >> +config BR2_RISCV_ISA_CUSTOM_RVV > > This option must depends on gcc-12. No, it's the other way round: it should force GCC 12, by selecting BR2_ARCH_NEEDS_GCC_AT_LEAST_12. Regards, Arnout > > Best regards, > Romain > >> + bool "Vector Instructions (V)" >> + select BR2_RISCV_ISA_RVV >> endif >> >> choice >> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv >> index f3bf2b3467..07a94aa6a4 100644 >> --- a/arch/arch.mk.riscv >> +++ b/arch/arch.mk.riscv >> @@ -26,5 +26,9 @@ endif >> ifeq ($(BR2_RISCV_ISA_RVC),y) >> GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c >> endif >> +ifeq ($(BR2_RISCV_ISA_RVV),y) >> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v >> +endif >> + >> >> endif > > _______________________________________________ > buildroot mailing list > buildroot@buildroot.org > https://lists.buildroot.org/mailman/listinfo/buildroot
Le 24/07/2022 à 11:25, Arnout Vandecappelle a écrit : > > > On 24/07/2022 10:08, Romain Naour wrote: >> Hello Abel, >> >> Le 23/07/2022 à 23:54, Abel Bernabeu a écrit : >>> This new setting will allow to test new toolchains already available >>> that support the vector extension (more patches coming soon). >> >> It seems that is the same series as v1: >> >> http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=* >> >> See 22.5.5. "Patch revision changelog" section for help. >> >> https://nightly.buildroot.org/manual.html#submitting-patches >> >>> >>> Signed-off-by: Abel Bernabeu <abel@x-silicon.com> >>> --- >>> arch/Config.in.riscv | 7 +++++++ >>> arch/arch.mk.riscv | 4 ++++ >>> 2 files changed, 11 insertions(+) >>> >>> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv >>> index 288ed833eb..e4dc936cf8 100644 >>> --- a/arch/Config.in.riscv >>> +++ b/arch/Config.in.riscv >>> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD >>> config BR2_RISCV_ISA_RVC >>> bool >>> +config BR2_RISCV_ISA_RVV >>> + bool >>> + >>> choice >>> prompt "Target Architecture Variant" >>> default BR2_riscv_g >>> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD >>> config BR2_RISCV_ISA_CUSTOM_RVC >>> bool "Compressed Instructions (C)" >>> select BR2_RISCV_ISA_RVC >>> + >>> +config BR2_RISCV_ISA_CUSTOM_RVV >> >> This option must depends on gcc-12. > > No, it's the other way round: it should force GCC 12, by selecting > BR2_ARCH_NEEDS_GCC_AT_LEAST_12. Indeed, Thomas commented on this yesterday [1] [1] http://lists.busybox.net/pipermail/buildroot/2022-July/646698.html Best regards, Romain > > Regards, > Arnout > >> >> Best regards, >> Romain >> >>> + bool "Vector Instructions (V)" >>> + select BR2_RISCV_ISA_RVV >>> endif >>> choice >>> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv >>> index f3bf2b3467..07a94aa6a4 100644 >>> --- a/arch/arch.mk.riscv >>> +++ b/arch/arch.mk.riscv >>> @@ -26,5 +26,9 @@ endif >>> ifeq ($(BR2_RISCV_ISA_RVC),y) >>> GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c >>> endif >>> +ifeq ($(BR2_RISCV_ISA_RVV),y) >>> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v >>> +endif >>> + >>> endif >> >> _______________________________________________ >> buildroot mailing list >> buildroot@buildroot.org >> https://lists.buildroot.org/mailman/listinfo/buildroot
Thanks, will do as suggested (forcing GCC 12 or newer when using the option). On Sun, Jul 24, 2022, 11:52 AM Romain Naour <romain.naour@smile.fr> wrote: > Le 24/07/2022 à 11:25, Arnout Vandecappelle a écrit : > > > > > > On 24/07/2022 10:08, Romain Naour wrote: > >> Hello Abel, > >> > >> Le 23/07/2022 à 23:54, Abel Bernabeu a écrit : > >>> This new setting will allow to test new toolchains already available > >>> that support the vector extension (more patches coming soon). > >> > >> It seems that is the same series as v1: > >> > >> > http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=* > >> > >> See 22.5.5. "Patch revision changelog" section for help. > >> > >> https://nightly.buildroot.org/manual.html#submitting-patches > >> > >>> > >>> Signed-off-by: Abel Bernabeu <abel@x-silicon.com> > >>> --- > >>> arch/Config.in.riscv | 7 +++++++ > >>> arch/arch.mk.riscv | 4 ++++ > >>> 2 files changed, 11 insertions(+) > >>> > >>> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv > >>> index 288ed833eb..e4dc936cf8 100644 > >>> --- a/arch/Config.in.riscv > >>> +++ b/arch/Config.in.riscv > >>> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD > >>> config BR2_RISCV_ISA_RVC > >>> bool > >>> +config BR2_RISCV_ISA_RVV > >>> + bool > >>> + > >>> choice > >>> prompt "Target Architecture Variant" > >>> default BR2_riscv_g > >>> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD > >>> config BR2_RISCV_ISA_CUSTOM_RVC > >>> bool "Compressed Instructions (C)" > >>> select BR2_RISCV_ISA_RVC > >>> + > >>> +config BR2_RISCV_ISA_CUSTOM_RVV > >> > >> This option must depends on gcc-12. > > > > No, it's the other way round: it should force GCC 12, by selecting > > BR2_ARCH_NEEDS_GCC_AT_LEAST_12. > > Indeed, Thomas commented on this yesterday [1] > > [1] http://lists.busybox.net/pipermail/buildroot/2022-July/646698.html > > Best regards, > Romain > > > > > > Regards, > > Arnout > > > >> > >> Best regards, > >> Romain > >> > >>> + bool "Vector Instructions (V)" > >>> + select BR2_RISCV_ISA_RVV > >>> endif > >>> choice > >>> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv > >>> index f3bf2b3467..07a94aa6a4 100644 > >>> --- a/arch/arch.mk.riscv > >>> +++ b/arch/arch.mk.riscv > >>> @@ -26,5 +26,9 @@ endif > >>> ifeq ($(BR2_RISCV_ISA_RVC),y) > >>> GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c > >>> endif > >>> +ifeq ($(BR2_RISCV_ISA_RVV),y) > >>> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v > >>> +endif > >>> + > >>> endif > >> > >> _______________________________________________ > >> buildroot mailing list > >> buildroot@buildroot.org > >> https://lists.buildroot.org/mailman/listinfo/buildroot > >
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 288ed833eb..e4dc936cf8 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD config BR2_RISCV_ISA_RVC bool +config BR2_RISCV_ISA_RVV + bool + choice prompt "Target Architecture Variant" default BR2_riscv_g @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD config BR2_RISCV_ISA_CUSTOM_RVC bool "Compressed Instructions (C)" select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV endif choice diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index f3bf2b3467..07a94aa6a4 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -26,5 +26,9 @@ endif ifeq ($(BR2_RISCV_ISA_RVC),y) GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c endif +ifeq ($(BR2_RISCV_ISA_RVV),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v +endif + endif
This new setting will allow to test new toolchains already available that support the vector extension (more patches coming soon). Signed-off-by: Abel Bernabeu <abel@x-silicon.com> --- arch/Config.in.riscv | 7 +++++++ arch/arch.mk.riscv | 4 ++++ 2 files changed, 11 insertions(+)