| Message ID | 20220723215448.2532160-1-abel@x-silicon.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/2] package/llvm: Support for RISC-V on the LLVM package | expand |
On Sat, 23 Jul 2022 23:54:47 +0200 Abel Bernabeu <abel@x-silicon.com> wrote: > The initial support for the LLVM package did not include RISC-V, and > needed to be added. > > There is a new configuration parameter added > (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that > the LLVM target and the architecture have different naming for RISC-V. > While the target for RISC-V is "RISCV" irrespective of the ISA being > 32 or 64 bits, the architecture does contain the number of bits > leading to "riscv32" and "riscv64". > > For previously supported architectures the naming for target and > architecture matched and thus this parameter had not been needed, but > it is now needed for RISC-V. > > Signed-off-by: Abel Bernabeu <abel@x-silicon.com> > --- > package/llvm/Config.in | 10 ++++++++++ > package/llvm/llvm.mk | 2 +- > 2 files changed, 11 insertions(+), 1 deletion(-) I have simplified the RISCV quirk by moving it to the llvm.mk file: # Build backend for target architecture. This include backends like # AMDGPU. We need to special case RISCV. ifneq ($(filter riscv%,$(LLVM_TARGET_ARCH)),) LLVM_TARGETS_TO_BUILD = RISCV else LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH) endif Applied with this change, thanks! Thomas
Thanks Thomas! On Tue, Aug 2, 2022 at 12:09 AM Thomas Petazzoni < thomas.petazzoni@bootlin.com> wrote: > On Sat, 23 Jul 2022 23:54:47 +0200 > Abel Bernabeu <abel@x-silicon.com> wrote: > > > The initial support for the LLVM package did not include RISC-V, and > > needed to be added. > > > > There is a new configuration parameter added > > (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that > > the LLVM target and the architecture have different naming for RISC-V. > > While the target for RISC-V is "RISCV" irrespective of the ISA being > > 32 or 64 bits, the architecture does contain the number of bits > > leading to "riscv32" and "riscv64". > > > > For previously supported architectures the naming for target and > > architecture matched and thus this parameter had not been needed, but > > it is now needed for RISC-V. > > > > Signed-off-by: Abel Bernabeu <abel@x-silicon.com> > > --- > > package/llvm/Config.in | 10 ++++++++++ > > package/llvm/llvm.mk | 2 +- > > 2 files changed, 11 insertions(+), 1 deletion(-) > > I have simplified the RISCV quirk by moving it to the llvm.mk file: > > # Build backend for target architecture. This include backends like > # AMDGPU. We need to special case RISCV. > ifneq ($(filter riscv%,$(LLVM_TARGET_ARCH)),) > LLVM_TARGETS_TO_BUILD = RISCV > else > LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH) > endif > > Applied with this change, thanks! > > Thomas > -- > Thomas Petazzoni, CTO, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com >
diff --git a/package/llvm/Config.in b/package/llvm/Config.in index c1887e36dd..61197fc588 100644 --- a/package/llvm/Config.in +++ b/package/llvm/Config.in @@ -4,12 +4,22 @@ config BR2_PACKAGE_LLVM_ARCH_SUPPORTS default y if BR2_x86_64 default y if BR2_aarch64 default y if BR2_arm || BR2_armeb + default y if BR2_riscv config BR2_PACKAGE_LLVM_TARGET_ARCH string default "AArch64" if BR2_aarch64 default "ARM" if BR2_arm || BR2_armeb default "X86" if BR2_i386 || BR2_x86_64 + default "riscv32" if BR2_riscv && !BR2_ARCH_IS_64 + default "riscv64" if BR2_riscv && BR2_ARCH_IS_64 + +config BR2_PACKAGE_LLVM_TARGETS_TO_BUILD + string + default "AArch64" if BR2_aarch64 + default "ARM" if BR2_arm || BR2_armeb + default "X86" if BR2_i386 || BR2_x86_64 + default "RISCV" if BR2_riscv config BR2_PACKAGE_LLVM bool "llvm" diff --git a/package/llvm/llvm.mk b/package/llvm/llvm.mk index 4670773ca3..dbf1f7b813 100644 --- a/package/llvm/llvm.mk +++ b/package/llvm/llvm.mk @@ -42,7 +42,7 @@ HOST_LLVM_CONF_OPTS += -DCMAKE_INSTALL_RPATH="$(HOST_DIR)/lib" LLVM_TARGET_ARCH = $(call qstrip,$(BR2_PACKAGE_LLVM_TARGET_ARCH)) # Build backend for target architecture. This include backends like AMDGPU. -LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH) +LLVM_TARGETS_TO_BUILD = $(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) HOST_LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))" LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
The initial support for the LLVM package did not include RISC-V, and needed to be added. There is a new configuration parameter added (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that the LLVM target and the architecture have different naming for RISC-V. While the target for RISC-V is "RISCV" irrespective of the ISA being 32 or 64 bits, the architecture does contain the number of bits leading to "riscv32" and "riscv64". For previously supported architectures the naming for target and architecture matched and thus this parameter had not been needed, but it is now needed for RISC-V. Signed-off-by: Abel Bernabeu <abel@x-silicon.com> --- package/llvm/Config.in | 10 ++++++++++ package/llvm/llvm.mk | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)