| Message ID | 20170720060032.19862-2-icenowy@aosc.io |
|---|---|
| State | Accepted |
| Commit | e37a1b17e71521ce9385e305a87948d7ca55b4d8 |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
在 2017-07-20 14:00，Icenowy Zheng 写道： > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls > the access to some clock/power related registers in PRCM. > > Current Linux kernel will access the CPUS (AR100) clock in the PRCM > block, so the PRCM should be switched to non-secure. > > Add code to switch the PRCM to non-secure. Ping. Maxime and Jagan, can you merge this patchset? This is necessary for R_CCU to work properly on H3. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/mach-sunxi/clock_sun6i.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm/mach-sunxi/clock_sun6i.c > b/arch/arm/mach-sunxi/clock_sun6i.c > index ec5b026ef5..870ff5b1e0 100644 > --- a/arch/arm/mach-sunxi/clock_sun6i.c > +++ b/arch/arm/mach-sunxi/clock_sun6i.c > @@ -66,11 +66,17 @@ void clock_init_sec(void) > #ifdef CONFIG_MACH_SUNXI_H3_H5 > struct sunxi_ccm_reg * const ccm = > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > + struct sunxi_prcm_reg * const prcm = > + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; > > setbits_le32(&ccm->ccu_sec_switch, > CCM_SEC_SWITCH_MBUS_NONSEC | > CCM_SEC_SWITCH_BUS_NONSEC | > CCM_SEC_SWITCH_PLL_NONSEC); > + setbits_le32(&prcm->prcm_sec_switch, > + PRCM_SEC_SWITCH_APB0_CLK_NONSEC | > + PRCM_SEC_SWITCH_PLL_CFG_NONSEC | > + PRCM_SEC_SWITCH_PWR_GATE_NONSEC); > #endif > }
On Wed, Jul 26, 2017 at 07:55:24PM +0800, icenowy@aosc.io wrote: > 在 2017-07-20 14:00，Icenowy Zheng 写道： > > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls > > the access to some clock/power related registers in PRCM. > > > > Current Linux kernel will access the CPUS (AR100) clock in the PRCM > > block, so the PRCM should be switched to non-secure. > > > > Add code to switch the PRCM to non-secure. > > Ping. > > Maxime and Jagan, can you merge this patchset? > > This is necessary for R_CCU to work properly on H3. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Maxime
On Thu, Jul 27, 2017 at 3:31 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Wed, Jul 26, 2017 at 07:55:24PM +0800, icenowy@aosc.io wrote: >> 在 2017-07-20 14:00，Icenowy Zheng 写道： >> > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls >> > the access to some clock/power related registers in PRCM. >> > >> > Current Linux kernel will access the CPUS (AR100) clock in the PRCM >> > block, so the PRCM should be switched to non-secure. >> > >> > Add code to switch the PRCM to non-secure. >> >> Ping. >> >> Maxime and Jagan, can you merge this patchset? >> >> This is necessary for R_CCU to work properly on H3. > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org>
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index ec5b026ef5..870ff5b1e0 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -66,11 +66,17 @@ void clock_init_sec(void) #ifdef CONFIG_MACH_SUNXI_H3_H5 struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; setbits_le32(&ccm->ccu_sec_switch, CCM_SEC_SWITCH_MBUS_NONSEC | CCM_SEC_SWITCH_BUS_NONSEC | CCM_SEC_SWITCH_PLL_NONSEC); + setbits_le32(&prcm->prcm_sec_switch, + PRCM_SEC_SWITCH_APB0_CLK_NONSEC | + PRCM_SEC_SWITCH_PLL_CFG_NONSEC | + PRCM_SEC_SWITCH_PWR_GATE_NONSEC); #endif }
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM. Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure. Add code to switch the PRCM to non-secure. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/mach-sunxi/clock_sun6i.c | 6 ++++++ 1 file changed, 6 insertions(+)