| Message ID | 1424818672-29501-9-git-send-email-nm@ti.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Rini |
| Headers | show |
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit : > Enable the OMAP3 specific errata code for 454179, 430973, 621766 > and while at it, remove legacy non-revision checked errata logic. > > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- > include/configs/ti_omap3_common.h | 6 ++++++ > 2 files changed, 6 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c > index 7ce30949a6c6..cc3a43341335 100644 > --- a/arch/arm/cpu/armv7/omap3/board.c > +++ b/arch/arm/cpu/armv7/omap3/board.c > @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; > > /* Declarations */ > extern omap3_sysinfo sysinfo; > -static void omap3_setup_aux_cr(void); > #ifndef CONFIG_SYS_L2CACHE_OFF > static void omap3_invalidate_l2_cache_secure(void); > #endif > @@ -246,9 +245,6 @@ void s_init(void) > > try_unlock_memory(); > > - /* Errata workarounds */ > - omap3_setup_aux_cr(); > - > #ifndef CONFIG_SYS_L2CACHE_OFF > /* Invalidate L2-cache from secure mode */ > omap3_invalidate_l2_cache_secure(); > @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) > } > } > > -static void omap3_setup_aux_cr(void) > -{ > - /* Workaround for Cortex-A8 errata: #454179 #430973 > - * Set "IBE" bit > - * Set "Disable Branch Size Mispredicts" bit > - * Workaround for erratum #621766 > - * Enable L1NEON bit > - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 > - */ > - omap3_update_aux_cr_secure(0xE0, 0); > -} > - > #ifndef CONFIG_SYS_L2CACHE_OFF > static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) > { > diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h > index f909f6b94a18..db15c12ddf53 100644 > --- a/include/configs/ti_omap3_common.h > +++ b/include/configs/ti_omap3_common.h Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection. > @@ -27,6 +27,12 @@ > # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) > #endif > > +/* Common ARM Erratas */ > +#define CONFIG_ARM_ARCH_CP15_ERRATA > +#define CONFIG_ARM_ERRATA_454179 > +#define CONFIG_ARM_ERRATA_430973 > +#define CONFIG_ARM_ERRATA_621766 > + > /* The chip has SDRC controller */ > #define CONFIG_SDRC >
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/25/15 13:19, Paul Kocialkowski wrote: > Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit : >> Enable the OMAP3 specific errata code for 454179, 430973, 621766 >> and while at it, remove legacy non-revision checked errata logic. >> >> Signed-off-by: Nishanth Menon <nm@ti.com> >> --- >> arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- >> include/configs/ti_omap3_common.h | 6 ++++++ >> 2 files changed, 6 insertions(+), 16 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c >> index 7ce30949a6c6..cc3a43341335 100644 >> --- a/arch/arm/cpu/armv7/omap3/board.c >> +++ b/arch/arm/cpu/armv7/omap3/board.c >> @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; >> >> /* Declarations */ >> extern omap3_sysinfo sysinfo; >> -static void omap3_setup_aux_cr(void); >> #ifndef CONFIG_SYS_L2CACHE_OFF >> static void omap3_invalidate_l2_cache_secure(void); >> #endif >> @@ -246,9 +245,6 @@ void s_init(void) >> >> try_unlock_memory(); >> >> - /* Errata workarounds */ >> - omap3_setup_aux_cr(); >> - >> #ifndef CONFIG_SYS_L2CACHE_OFF >> /* Invalidate L2-cache from secure mode */ >> omap3_invalidate_l2_cache_secure(); >> @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) >> } >> } >> >> -static void omap3_setup_aux_cr(void) >> -{ >> - /* Workaround for Cortex-A8 errata: #454179 #430973 >> - * Set "IBE" bit >> - * Set "Disable Branch Size Mispredicts" bit >> - * Workaround for erratum #621766 >> - * Enable L1NEON bit >> - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 >> - */ >> - omap3_update_aux_cr_secure(0xE0, 0); >> -} >> - >> #ifndef CONFIG_SYS_L2CACHE_OFF >> static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) >> { >> diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h >> index f909f6b94a18..db15c12ddf53 100644 >> --- a/include/configs/ti_omap3_common.h >> +++ b/include/configs/ti_omap3_common.h > > Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You > can find a complete list of all the configs that need those options > enabled from my first patch on that topic: > http://lists.denx.de/pipermail/u-boot/2015-February/205809.html > > I guess it's better to enable those on all the currently-supported omap3 > platforms: that's the way it was so far and it won't hurt in cases it's > not needed thanks to the revision detection. Or... I think this patch might be a good enough argument to request people switch to include ti_omap3_common.h instead of duplicating it in private configs... Don't you think? > >> @@ -27,6 +27,12 @@ >> # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) >> #endif >> >> +/* Common ARM Erratas */ >> +#define CONFIG_ARM_ARCH_CP15_ERRATA >> +#define CONFIG_ARM_ERRATA_454179 >> +#define CONFIG_ARM_ERRATA_430973 >> +#define CONFIG_ARM_ERRATA_621766 >> + >> /* The chip has SDRC controller */ >> #define CONFIG_SDRC >> > > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > - -- Regards, Igor. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJU7bKeAAoJEBDE8YO64Efa/FUP/03ShzfpDHCl4aaSSoY8zLgl K/C3eeK2EFKxS/CDCQCV4KGk/lXdIbmx2BHH9ErKXwUmMp63QZUo6EzLjks9CeKl HZ9yBVxr9e3X2ztvZUpBWc5C6YpFxRfO9f5Q3GeLsv+217dccLRiomTVYlKLXQmJ VUHofOfKlF5b0sQxcAI+wONNkhsSX5rVHmcm6NziC4w8ZedJy5zer6rTfMY54WPx Z3jDKkvWK5DWOXNEpu0OVRC1RlKB6kqgedyaQTqwDLpL6Hz7oF3KeVJTKxbQgOPy 8vh2PeLX0AERL1hz6fEaG6pFnAT/V/4uEmczBAgAnCTr6NiCpC2QtlC1PAWTkg/c 4NPz/z5HM4o2cTpqI9Yc6oWExqZzANQLBJYtm8bD2pkUMA/RbVuLugnOka9trVFw MHRqOBlAtq2tchvLZIhzQrh+bb5KsKWNFdoIkCFXUwYdqasMhxoW2G/4fDsf0oeL q1vQV0LJp/qysLzz8u5603cFR7IvFKWSr4wP95YvlEhx6BGsKPXu0QeTVfpsPHZX L4tP1X/wM10XGN2HGenz2FimtaUUJZTxHzj18ucMfyLs0hAfT981auyvyMLR5Up2 bFlB6b93y1BpM0DxpmgcuA77gLQL9jNKTyH76W/AQysOikSQ8JrSZg52zS3X0m6Q QJ4jdRF+EAY/Eh/fIni0 =q25V -----END PGP SIGNATURE-----
Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit : > On 02/25/15 13:19, Paul Kocialkowski wrote: > > Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit : > >> Enable the OMAP3 specific errata code for 454179, 430973, 621766 > >> and while at it, remove legacy non-revision checked errata logic. > >> > >> Signed-off-by: Nishanth Menon <nm@ti.com> > >> --- > >> arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- > >> include/configs/ti_omap3_common.h | 6 ++++++ > >> 2 files changed, 6 insertions(+), 16 deletions(-) > >> > >> diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c > >> index 7ce30949a6c6..cc3a43341335 100644 > >> --- a/arch/arm/cpu/armv7/omap3/board.c > >> +++ b/arch/arm/cpu/armv7/omap3/board.c > >> @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; > >> > >> /* Declarations */ > >> extern omap3_sysinfo sysinfo; > >> -static void omap3_setup_aux_cr(void); > >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> static void omap3_invalidate_l2_cache_secure(void); > >> #endif > >> @@ -246,9 +245,6 @@ void s_init(void) > >> > >> try_unlock_memory(); > >> > >> - /* Errata workarounds */ > >> - omap3_setup_aux_cr(); > >> - > >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> /* Invalidate L2-cache from secure mode */ > >> omap3_invalidate_l2_cache_secure(); > >> @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) > >> } > >> } > >> > >> -static void omap3_setup_aux_cr(void) > >> -{ > >> - /* Workaround for Cortex-A8 errata: #454179 #430973 > >> - * Set "IBE" bit > >> - * Set "Disable Branch Size Mispredicts" bit > >> - * Workaround for erratum #621766 > >> - * Enable L1NEON bit > >> - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 > >> - */ > >> - omap3_update_aux_cr_secure(0xE0, 0); > >> -} > >> - > >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) > >> { > >> diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h > >> index f909f6b94a18..db15c12ddf53 100644 > >> --- a/include/configs/ti_omap3_common.h > >> +++ b/include/configs/ti_omap3_common.h > > > > Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You > > can find a complete list of all the configs that need those options > > enabled from my first patch on that topic: > > http://lists.denx.de/pipermail/u-boot/2015-February/205809.html > > > > I guess it's better to enable those on all the currently-supported omap3 > > platforms: that's the way it was so far and it won't hurt in cases it's > > not needed thanks to the revision detection. > > Or... > I think this patch might be a good enough argument to request people > switch to include ti_omap3_common.h instead of duplicating it in > private configs... > > Don't you think? The way I see it, ti_omap3_common.h is common for OMAP3 boards made by TI. A few things there are not generic to omap3 in general (e.g. not every board uses the U-Boot SPL, or UART3 for console). However, I agree it would be beneficial to have an omap3_common.h config with the options that are expected to be shared accross every possible omap3 device (and with a few clever ifdef so that the minimum has to be set in the including board configs). I could try to come up with such a config if you wish, but I'm afraid I'm not the most qualified person to do this (I only have a single omap3 device). > >> @@ -27,6 +27,12 @@ > >> # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) > >> #endif > >> > >> +/* Common ARM Erratas */ > >> +#define CONFIG_ARM_ARCH_CP15_ERRATA > >> +#define CONFIG_ARM_ERRATA_454179 > >> +#define CONFIG_ARM_ERRATA_430973 > >> +#define CONFIG_ARM_ERRATA_621766 > >> + > >> /* The chip has SDRC controller */ > >> #define CONFIG_SDRC > >> > > > > > > > > _______________________________________________ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > > >
On Wed, Feb 25, 2015 at 6:27 AM, Paul Kocialkowski <contact@paulk.fr> wrote: > Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit : >> On 02/25/15 13:19, Paul Kocialkowski wrote: >> > Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit : >> >> Enable the OMAP3 specific errata code for 454179, 430973, 621766 >> >> and while at it, remove legacy non-revision checked errata logic. >> >> >> >> Signed-off-by: Nishanth Menon <nm@ti.com> >> >> --- >> >> arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- >> >> include/configs/ti_omap3_common.h | 6 ++++++ >> >> 2 files changed, 6 insertions(+), 16 deletions(-) >> >> >> >> diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c >> >> index 7ce30949a6c6..cc3a43341335 100644 >> >> --- a/arch/arm/cpu/armv7/omap3/board.c >> >> +++ b/arch/arm/cpu/armv7/omap3/board.c >> >> @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; >> >> >> >> /* Declarations */ >> >> extern omap3_sysinfo sysinfo; >> >> -static void omap3_setup_aux_cr(void); >> >> #ifndef CONFIG_SYS_L2CACHE_OFF >> >> static void omap3_invalidate_l2_cache_secure(void); >> >> #endif >> >> @@ -246,9 +245,6 @@ void s_init(void) >> >> >> >> try_unlock_memory(); >> >> >> >> - /* Errata workarounds */ >> >> - omap3_setup_aux_cr(); >> >> - >> >> #ifndef CONFIG_SYS_L2CACHE_OFF >> >> /* Invalidate L2-cache from secure mode */ >> >> omap3_invalidate_l2_cache_secure(); >> >> @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) >> >> } >> >> } >> >> >> >> -static void omap3_setup_aux_cr(void) >> >> -{ >> >> - /* Workaround for Cortex-A8 errata: #454179 #430973 >> >> - * Set "IBE" bit >> >> - * Set "Disable Branch Size Mispredicts" bit >> >> - * Workaround for erratum #621766 >> >> - * Enable L1NEON bit >> >> - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 >> >> - */ >> >> - omap3_update_aux_cr_secure(0xE0, 0); >> >> -} >> >> - >> >> #ifndef CONFIG_SYS_L2CACHE_OFF >> >> static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) >> >> { >> >> diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h >> >> index f909f6b94a18..db15c12ddf53 100644 >> >> --- a/include/configs/ti_omap3_common.h >> >> +++ b/include/configs/ti_omap3_common.h >> > >> > Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You >> > can find a complete list of all the configs that need those options >> > enabled from my first patch on that topic: >> > http://lists.denx.de/pipermail/u-boot/2015-February/205809.html >> > >> > I guess it's better to enable those on all the currently-supported omap3 >> > platforms: that's the way it was so far and it won't hurt in cases it's >> > not needed thanks to the revision detection. >> >> Or... >> I think this patch might be a good enough argument to request people >> switch to include ti_omap3_common.h instead of duplicating it in >> private configs... >> >> Don't you think? > > The way I see it, ti_omap3_common.h is common for OMAP3 boards made by > TI. A few things there are not generic to omap3 in general (e.g. not > every board uses the U-Boot SPL, or UART3 for console). > > However, I agree it would be beneficial to have an omap3_common.h config > with the options that are expected to be shared accross every possible > omap3 device (and with a few clever ifdef so that the minimum has to be > set in the including board configs). > > I could try to come up with such a config if you wish, but I'm afraid > I'm not the most qualified person to do this (I only have a single omap3 > device). > I am planning on a V3 based on trying to converge exynos and TI platforms into a common code base. I will stick with ti_*_common.h headers for now, we will keep all the other headers updated for the moment. I do stand with the opinion that we should all be using the same ti_omap3_common header for all platforms using the same SoC... but that could be done as follow on patches. That said, Paul, if you could contribute patches to the effect of integrating all these platforms to ti_*_common.h, that'd be great. -- Regards, Nishanth Menon
Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a écrit : > On Wed, Feb 25, 2015 at 6:27 AM, Paul Kocialkowski <contact@paulk.fr> wrote: > > Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit : > >> On 02/25/15 13:19, Paul Kocialkowski wrote: > >> > Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit : > >> >> Enable the OMAP3 specific errata code for 454179, 430973, 621766 > >> >> and while at it, remove legacy non-revision checked errata logic. > >> >> > >> >> Signed-off-by: Nishanth Menon <nm@ti.com> > >> >> --- > >> >> arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- > >> >> include/configs/ti_omap3_common.h | 6 ++++++ > >> >> 2 files changed, 6 insertions(+), 16 deletions(-) > >> >> > >> >> diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c > >> >> index 7ce30949a6c6..cc3a43341335 100644 > >> >> --- a/arch/arm/cpu/armv7/omap3/board.c > >> >> +++ b/arch/arm/cpu/armv7/omap3/board.c > >> >> @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; > >> >> > >> >> /* Declarations */ > >> >> extern omap3_sysinfo sysinfo; > >> >> -static void omap3_setup_aux_cr(void); > >> >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> >> static void omap3_invalidate_l2_cache_secure(void); > >> >> #endif > >> >> @@ -246,9 +245,6 @@ void s_init(void) > >> >> > >> >> try_unlock_memory(); > >> >> > >> >> - /* Errata workarounds */ > >> >> - omap3_setup_aux_cr(); > >> >> - > >> >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> >> /* Invalidate L2-cache from secure mode */ > >> >> omap3_invalidate_l2_cache_secure(); > >> >> @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) > >> >> } > >> >> } > >> >> > >> >> -static void omap3_setup_aux_cr(void) > >> >> -{ > >> >> - /* Workaround for Cortex-A8 errata: #454179 #430973 > >> >> - * Set "IBE" bit > >> >> - * Set "Disable Branch Size Mispredicts" bit > >> >> - * Workaround for erratum #621766 > >> >> - * Enable L1NEON bit > >> >> - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 > >> >> - */ > >> >> - omap3_update_aux_cr_secure(0xE0, 0); > >> >> -} > >> >> - > >> >> #ifndef CONFIG_SYS_L2CACHE_OFF > >> >> static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) > >> >> { > >> >> diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h > >> >> index f909f6b94a18..db15c12ddf53 100644 > >> >> --- a/include/configs/ti_omap3_common.h > >> >> +++ b/include/configs/ti_omap3_common.h > >> > > >> > Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You > >> > can find a complete list of all the configs that need those options > >> > enabled from my first patch on that topic: > >> > http://lists.denx.de/pipermail/u-boot/2015-February/205809.html > >> > > >> > I guess it's better to enable those on all the currently-supported omap3 > >> > platforms: that's the way it was so far and it won't hurt in cases it's > >> > not needed thanks to the revision detection. > >> > >> Or... > >> I think this patch might be a good enough argument to request people > >> switch to include ti_omap3_common.h instead of duplicating it in > >> private configs... > >> > >> Don't you think? > > > > The way I see it, ti_omap3_common.h is common for OMAP3 boards made by > > TI. A few things there are not generic to omap3 in general (e.g. not > > every board uses the U-Boot SPL, or UART3 for console). > > > > However, I agree it would be beneficial to have an omap3_common.h config > > with the options that are expected to be shared accross every possible > > omap3 device (and with a few clever ifdef so that the minimum has to be > > set in the including board configs). > > > > I could try to come up with such a config if you wish, but I'm afraid > > I'm not the most qualified person to do this (I only have a single omap3 > > device). > I am planning on a V3 based on trying to converge exynos and TI > platforms into a common code base. I will stick with ti_*_common.h > headers for now, we will keep all the other headers updated for the > moment. I do stand with the opinion that we should all be using the > same ti_omap3_common header for all platforms using the same SoC... > but that could be done as follow on patches. > > That said, Paul, if you could contribute patches to the effect of > integrating all these platforms to ti_*_common.h, that'd be great. I will try to come up with a common configuration for omap3 (and possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I don't feel it's relevant to mention the chip manufacturer there, especially when it's not used anywhere else in the tree (except for the boards that are actually procuced by TI such as the evms, etc).
On 02/25/2015 03:23 PM, Paul Kocialkowski wrote: > Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a [...] >> That said, Paul, if you could contribute patches to the effect of >> integrating all these platforms to ti_*_common.h, that'd be great. > > I will try to come up with a common configuration for omap3 (and > possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I > don't feel it's relevant to mention the chip manufacturer there, > especially when it's not used anywhere else in the tree (except for the > boards that are actually procuced by TI such as the evms, etc). > I think we have maintained ti_ prefix for omap3,4,5 etc.. might make sense to retain that.. but then, I am no decision maker in that regards, I suggest posting a proposal and seeing feedback folks have w.r.t. -- Regards, Nishanth Menon
Le mercredi 25 février 2015 à 23:11 -0600, Nishanth Menon a écrit : > On 02/25/2015 03:23 PM, Paul Kocialkowski wrote: > > Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a > [...] > >> That said, Paul, if you could contribute patches to the effect of > >> integrating all these platforms to ti_*_common.h, that'd be great. > > > > I will try to come up with a common configuration for omap3 (and > > possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I > > don't feel it's relevant to mention the chip manufacturer there, > > especially when it's not used anywhere else in the tree (except for the > > boards that are actually procuced by TI such as the evms, etc). > > > I think we have maintained ti_ prefix for omap3,4,5 etc.. might make > sense to retain that.. but then, I am no decision maker in that regards, > I suggest posting a proposal and seeing feedback folks have w.r.t. I have started looking at the situation for am33xx, omap3, omap4 and omap5 and I'll post a RFC at some point in the near future. I'm a bit busy right now and this is not high priority since your latest series includes all the configs for the affected omap3 boards.
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void) try_unlock_memory(); - /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_setup_aux_cr(void) -{ - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); -} - #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,6 +27,12 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif +/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + /* The chip has SDRC controller */ #define CONFIG_SDRC
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic. Signed-off-by: Nishanth Menon <nm@ti.com> --- arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)