| Message ID | 1424719005-18838-1-git-send-email-contact@paulk.fr |
|---|---|
| State | Superseded |
| Delegated to: | Tom Rini |
| Headers | show |
On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: > Not every version and revision of the Cortex-A8 ARM core requires the same > errata workarounds. In addition, enabling those requires to have similar > workarounds enabled in the kernel or it will cause numerous segmentation faults. > > This enables those workarounds when they are needed, according to what is done > in Linux. > > Follow-up to the discussion from July 2013: > http://lists.denx.de/pipermail/u-boot/2013-July/158377.html > > Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Nishanth, any comments here, since you've been thinking about errata stuff lately? Thanks! Reviewed-by: Tom Rini <trini@ti.com>
On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini <trini@ti.com> wrote: > On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: > >> Not every version and revision of the Cortex-A8 ARM core requires the same >> errata workarounds. In addition, enabling those requires to have similar >> workarounds enabled in the kernel or it will cause numerous segmentation faults. >> >> This enables those workarounds when they are needed, according to what is done >> in Linux. >> >> Follow-up to the discussion from July 2013: >> http://lists.denx.de/pipermail/u-boot/2013-July/158377.html >> >> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> > > Nishanth, any comments here, since you've been thinking about errata > stuff lately? Thanks! > > Reviewed-by: Tom Rini <trini@ti.com> > I would probably go with v7 start code triggering the logic. even though the secure logic is probably unique.. something like CONFIG_ARM_ARCH_CP15_ERRATA or like
Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit : > On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini <trini@ti.com> wrote: > > On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: > > > >> Not every version and revision of the Cortex-A8 ARM core requires the same > >> errata workarounds. In addition, enabling those requires to have similar > >> workarounds enabled in the kernel or it will cause numerous segmentation faults. > >> > >> This enables those workarounds when they are needed, according to what is done > >> in Linux. > >> > >> Follow-up to the discussion from July 2013: > >> http://lists.denx.de/pipermail/u-boot/2013-July/158377.html > >> > >> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> > > > > Nishanth, any comments here, since you've been thinking about errata > > stuff lately? Thanks! > > > > Reviewed-by: Tom Rini <trini@ti.com> > > > > I would probably go with v7 start code triggering the logic. even > though the secure logic is probably unique.. It does seem like the secure logic is specific to the OMAP, even though the GP part (omap3_gp_romcode_call) seems to be generic. I don't think it would fit well in common v7 code and overall, I don't think I have sufficient knowledge of those issues to take the decision to move that code around. Hence, I'll keep my proposal to what it is now, and let someone else move the code around in the future if they feel the need to. > something like CONFIG_ARM_ARCH_CP15_ERRATA or like
On Tue, Feb 24, 2015 at 6:02 AM, Paul Kocialkowski <contact@paulk.fr> wrote: > Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit : >> On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini <trini@ti.com> wrote: >> > On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: >> > >> >> Not every version and revision of the Cortex-A8 ARM core requires the same >> >> errata workarounds. In addition, enabling those requires to have similar >> >> workarounds enabled in the kernel or it will cause numerous segmentation faults. >> >> >> >> This enables those workarounds when they are needed, according to what is done >> >> in Linux. >> >> >> >> Follow-up to the discussion from July 2013: >> >> http://lists.denx.de/pipermail/u-boot/2013-July/158377.html >> >> >> >> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> >> > >> > Nishanth, any comments here, since you've been thinking about errata >> > stuff lately? Thanks! >> > >> > Reviewed-by: Tom Rini <trini@ti.com> >> > >> >> I would probably go with v7 start code triggering the logic. even >> though the secure logic is probably unique.. > > It does seem like the secure logic is specific to the OMAP, even though > the GP part (omap3_gp_romcode_call) seems to be generic. > > I don't think it would fit well in common v7 code and overall, I don't > think I have sufficient knowledge of those issues to take the decision > to move that code around. > > Hence, I'll keep my proposal to what it is now, and let someone else > move the code around in the future if they feel the need to. Do you mind if i took a shot at it? would be great if you could test the same.
Le mardi 24 février 2015 à 09:22 -0600, Nishanth Menon a écrit : > On Tue, Feb 24, 2015 at 6:02 AM, Paul Kocialkowski <contact@paulk.fr> wrote: > > Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit : > >> On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini <trini@ti.com> wrote: > >> > On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: > >> > > >> >> Not every version and revision of the Cortex-A8 ARM core requires the same > >> >> errata workarounds. In addition, enabling those requires to have similar > >> >> workarounds enabled in the kernel or it will cause numerous segmentation faults. > >> >> > >> >> This enables those workarounds when they are needed, according to what is done > >> >> in Linux. > >> >> > >> >> Follow-up to the discussion from July 2013: > >> >> http://lists.denx.de/pipermail/u-boot/2013-July/158377.html > >> >> > >> >> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> > >> > > >> > Nishanth, any comments here, since you've been thinking about errata > >> > stuff lately? Thanks! > >> > > >> > Reviewed-by: Tom Rini <trini@ti.com> > >> > > >> > >> I would probably go with v7 start code triggering the logic. even > >> though the secure logic is probably unique.. > > > > It does seem like the secure logic is specific to the OMAP, even though > > the GP part (omap3_gp_romcode_call) seems to be generic. > > > > I don't think it would fit well in common v7 code and overall, I don't > > think I have sufficient knowledge of those issues to take the decision > > to move that code around. > > > > Hence, I'll keep my proposal to what it is now, and let someone else > > move the code around in the future if they feel the need to. > > Do you mind if i took a shot at it? would be great if you could test the same. Alright, please go ahead! I'm available to test any patch on my omap 3630 device.
On 02/24/2015 10:09 AM, Paul Kocialkowski wrote: > Le mardi 24 février 2015 à 09:22 -0600, Nishanth Menon a écrit : >> On Tue, Feb 24, 2015 at 6:02 AM, Paul Kocialkowski <contact@paulk.fr> wrote: >>> Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit : >>>> On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini <trini@ti.com> wrote: >>>>> On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote: >>>>> >>>>>> Not every version and revision of the Cortex-A8 ARM core requires the same >>>>>> errata workarounds. In addition, enabling those requires to have similar >>>>>> workarounds enabled in the kernel or it will cause numerous segmentation faults. >>>>>> >>>>>> This enables those workarounds when they are needed, according to what is done >>>>>> in Linux. >>>>>> >>>>>> Follow-up to the discussion from July 2013: >>>>>> http://lists.denx.de/pipermail/u-boot/2013-July/158377.html >>>>>> >>>>>> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> >>>>> >>>>> Nishanth, any comments here, since you've been thinking about errata >>>>> stuff lately? Thanks! >>>>> >>>>> Reviewed-by: Tom Rini <trini@ti.com> >>>>> >>>> >>>> I would probably go with v7 start code triggering the logic. even >>>> though the secure logic is probably unique.. >>> >>> It does seem like the secure logic is specific to the OMAP, even though >>> the GP part (omap3_gp_romcode_call) seems to be generic. >>> >>> I don't think it would fit well in common v7 code and overall, I don't >>> think I have sufficient knowledge of those issues to take the decision >>> to move that code around. >>> >>> Hence, I'll keep my proposal to what it is now, and let someone else >>> move the code around in the future if they feel the need to. >> >> Do you mind if i took a shot at it? would be great if you could test the same. > > Alright, please go ahead! I'm available to test any patch on my omap > 3630 device. > Alright, the series should now include OMAP3 as well.. Sorry about confusion when list blocked me for too many cc folks etc.. anyways.. https://patchwork.ozlabs.org/patch/443261/ https://patchwork.ozlabs.org/patch/443264/ https://patchwork.ozlabs.org/patch/443268/ https://patchwork.ozlabs.org/patch/443265/ https://patchwork.ozlabs.org/patch/443263/ https://patchwork.ozlabs.org/patch/443262/ https://patchwork.ozlabs.org/patch/443267/ https://patchwork.ozlabs.org/patch/443266/ https://patchwork.ozlabs.org/patch/443260/
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7..3c198fc 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -431,14 +431,31 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) static void omap3_setup_aux_cr(void) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 + u32 id, revision, variant; + u32 bits = 0; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (id)); + + variant = (id & 0xf00000) >> 20; + revision = id & 0x0f; + + /* + * Workaround for Cortex-A8 errata #454179, #430973 + * Set IBE bit + * Set Disable Branch Size Mispredicts (DBSM) bit + */ + if (variant < 2) + bits |= (1 << 6) | (1 << 7); + + /* + * Workaround for Cortex-A8 erratum #621766 * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 */ - omap3_update_aux_cr_secure(0xE0, 0); + if (variant == 2 && revision == 0) + bits |= (1 << 5); + + if (bits != 0) + omap3_update_aux_cr_secure(bits, 0); } #ifndef CONFIG_SYS_L2CACHE_OFF
Not every version and revision of the Cortex-A8 ARM core requires the same errata workarounds. In addition, enabling those requires to have similar workarounds enabled in the kernel or it will cause numerous segmentation faults. This enables those workarounds when they are needed, according to what is done in Linux. Follow-up to the discussion from July 2013: http://lists.denx.de/pipermail/u-boot/2013-July/158377.html Signed-off-by: Paul Kocialkowski <contact@paulk.fr> --- arch/arm/cpu/armv7/omap3/board.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-)