| Message ID | 1424419040-28768-4-git-send-email-akshay.s@samsung.com |
|---|---|
| State | Accepted |
| Delegated to: | Minkyu Kang |
| Headers | show |
On 13:27-20150220, Akshay Saraswat wrote: > This patch adds workaround for ARM errata 798870 which says > "If back-to-back speculative cache line fills (fill A and fill B) are > issued from the L1 data cache of a CPU to the L2 cache, the second > request (fill B) is then cancelled, and the second request would have > detected a hazard against a recent write or eviction (write B) to the > same cache line as fill B then the L2 logic might deadlock." > > Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> > Reviewed-by: Simon Glass <sjg@chromium.org> > Tested-by: Simon Glass <sjg@chromium.org> > --- > Changes since v3: > - Added errata number in comment. > - Moved changes to arm generic armv7.h > > Changes since v2: > - No change. > > Changes since v1: > - Added Reviewed-by & Tested-by. > - Added space before */ on line # 40. > > arch/arm/include/asm/armv7.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h > index a13da23..a2040b7 100644 > --- a/arch/arm/include/asm/armv7.h > +++ b/arch/arm/include/asm/armv7.h > @@ -69,6 +69,22 @@ > #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) > #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) > > +/* > + * Workaround for ARM errata # 798870 > + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been > + * stalled for 1024 cycles to verify that its hazard condition still exists. > + */ > +static inline void v7_enable_l2_hazard_detect(void) > +{ > + uint32_t val; > + > + /* L2ACTLR[7]: Enable hazard detect timeout */ > + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); > + val |= (1 << 7); > + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by u-boot. has to go to secure world using smc call. > +} > + > +void v7_en_l2_hazard_detect(void); > void v7_outer_cache_enable(void); > void v7_outer_cache_disable(void); > void v7_outer_cache_flush_all(void); How about this - using the series: https://patchwork.ozlabs.org/patch/443261/ https://patchwork.ozlabs.org/patch/443264/ https://patchwork.ozlabs.org/patch/443268/ https://patchwork.ozlabs.org/patch/443265/ https://patchwork.ozlabs.org/patch/443263/ https://patchwork.ozlabs.org/patch/443262/ https://patchwork.ozlabs.org/patch/443267/ https://patchwork.ozlabs.org/patch/443266/ https://patchwork.ozlabs.org/patch/443260/
Nishanth Menon <nm@ti.com> writes: > On 13:27-20150220, Akshay Saraswat wrote: >> This patch adds workaround for ARM errata 798870 which says >> "If back-to-back speculative cache line fills (fill A and fill B) are >> issued from the L1 data cache of a CPU to the L2 cache, the second >> request (fill B) is then cancelled, and the second request would have >> detected a hazard against a recent write or eviction (write B) to the >> same cache line as fill B then the L2 logic might deadlock." >> >> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> >> Reviewed-by: Simon Glass <sjg@chromium.org> >> Tested-by: Simon Glass <sjg@chromium.org> >> --- >> Changes since v3: >> - Added errata number in comment. >> - Moved changes to arm generic armv7.h >> >> Changes since v2: >> - No change. >> >> Changes since v1: >> - Added Reviewed-by & Tested-by. >> - Added space before */ on line # 40. >> >> arch/arm/include/asm/armv7.h | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h >> index a13da23..a2040b7 100644 >> --- a/arch/arm/include/asm/armv7.h >> +++ b/arch/arm/include/asm/armv7.h >> @@ -69,6 +69,22 @@ >> #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) >> #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) >> >> +/* >> + * Workaround for ARM errata # 798870 >> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been >> + * stalled for 1024 cycles to verify that its hazard condition still exists. >> + */ >> +static inline void v7_enable_l2_hazard_detect(void) >> +{ >> + uint32_t val; >> + >> + /* L2ACTLR[7]: Enable hazard detect timeout */ >> + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); >> + val |= (1 << 7); >> + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); > > This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by > u-boot. has to go to secure world using smc call. > I believe the same may be true even on some exynos5 platforms with secure firmware (e.g. exynos5422-odroid-xu3). Kevin
On 02/25/2015 01:55 PM, Kevin Hilman wrote: > Nishanth Menon <nm@ti.com> writes: > >> On 13:27-20150220, Akshay Saraswat wrote: >>> This patch adds workaround for ARM errata 798870 which says >>> "If back-to-back speculative cache line fills (fill A and fill B) are >>> issued from the L1 data cache of a CPU to the L2 cache, the second >>> request (fill B) is then cancelled, and the second request would have >>> detected a hazard against a recent write or eviction (write B) to the >>> same cache line as fill B then the L2 logic might deadlock." >>> >>> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> >>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> >>> Reviewed-by: Simon Glass <sjg@chromium.org> >>> Tested-by: Simon Glass <sjg@chromium.org> >>> --- >>> Changes since v3: >>> - Added errata number in comment. >>> - Moved changes to arm generic armv7.h >>> >>> Changes since v2: >>> - No change. >>> >>> Changes since v1: >>> - Added Reviewed-by & Tested-by. >>> - Added space before */ on line # 40. >>> >>> arch/arm/include/asm/armv7.h | 16 ++++++++++++++++ >>> 1 file changed, 16 insertions(+) >>> >>> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h >>> index a13da23..a2040b7 100644 >>> --- a/arch/arm/include/asm/armv7.h >>> +++ b/arch/arm/include/asm/armv7.h >>> @@ -69,6 +69,22 @@ >>> #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) >>> #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) >>> >>> +/* >>> + * Workaround for ARM errata # 798870 >>> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been >>> + * stalled for 1024 cycles to verify that its hazard condition still exists. >>> + */ >>> +static inline void v7_enable_l2_hazard_detect(void) >>> +{ >>> + uint32_t val; >>> + >>> + /* L2ACTLR[7]: Enable hazard detect timeout */ >>> + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); >>> + val |= (1 << 7); >>> + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); >> >> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by >> u-boot. has to go to secure world using smc call. >> > > I believe the same may be true even on some exynos5 platforms with > secure firmware (e.g. exynos5422-odroid-xu3). I hope http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213207 should probably help handle for secure and non-secure devices by some soc specific glue layer (something similar to omap3 perhaps).. I am not too familiar with exynos family to comment better.
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23..a2040b7 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -69,6 +69,22 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +/* + * Workaround for ARM errata # 798870 + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been + * stalled for 1024 cycles to verify that its hazard condition still exists. + */ +static inline void v7_enable_l2_hazard_detect(void) +{ + uint32_t val; + + /* L2ACTLR[7]: Enable hazard detect timeout */ + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); + val |= (1 << 7); + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); +} + +void v7_en_l2_hazard_detect(void); void v7_outer_cache_enable(void); void v7_outer_cache_disable(void); void v7_outer_cache_flush_all(void);